5d71064f60
shader_decode: Implement BFE
7 years ago
6d21611470
shader_decode: Implement FSET
7 years ago
22618d59df
shader_decode: Implement F2I
7 years ago
d373f13b8a
shader_decode: Implement I2F
7 years ago
e456e2c1f3
shader_decode: Implement F2F
7 years ago
d72735028d
shader_decode: Stub DEPBAR
7 years ago
6f10bfaa08
shader_decode: Implement SSY and SYNC
7 years ago
fc0b3219fd
shader_decode: Implement PSETP
7 years ago
839abe1408
shader_decode: Implement TMML
7 years ago
0425f475d5
shader_decode: Implement TEX and TXQ
7 years ago
c8d0937ae5
shader_decode: Implement TEXS (F32)
7 years ago
ec28320c14
shader_decode: Implement FSETP
7 years ago
3aa53e3c01
shader_decode: Partially implement BRA
7 years ago
0398f7d0a4
shader_decode: Implement IPA
7 years ago
bc5992fccb
shader_decode: Implement EXIT
7 years ago
efda47fa37
shader_decode: Implement ST_A
7 years ago
0673f11907
shader_decode: Implement LD_A
7 years ago
b7b08104e5
shader_decode: Implement FADD32I
7 years ago
0b08169b9d
shader_decode: Implement FMUL32_IMM
7 years ago
4e1582eed1
shader_decode: Implement MOV32_IMM
7 years ago
b558235ec6
shader_decode: Stub RRO_C, RRO_R and RRO_IMM
7 years ago
cb19ed0316
shader_decode: Implement FMNMX_C, FMNMX_R and FMNMX_IMM
7 years ago
12d5281eff
shader_decode: Implement MUFU
7 years ago
bdafb25d16
shader_decode: Implement FADD_C, FADD_R and FADD_IMM
7 years ago
aa64616724
shader_decode: Implement FMUL_C, FMUL_R and FMUL_IMM
7 years ago
42b7053aa4
shader_decode: Implement MOV_C and MOV_R
7 years ago
5678498dfd
glsl_decompiler: Implementation
7 years ago
74ee18de5e
shader_ir: Add condition code helper
7 years ago
283dd9fb61
shader_ir: Add predicate combiner helper
7 years ago
d28033adca
shader_ir: Add comparison helpers
7 years ago
c0d053482c
shader_ir: Add half float helpers
7 years ago
e46dd3ce5f
shader_ir: Add integer helpers
7 years ago
b91929bf10
shader_ir: Add float helpers
7 years ago
83e750c9ae
shader_ir: Add setters
7 years ago
394f906044
shader_ir: Add local memory getters
7 years ago
311d1af657
shader_ir: Add internal flag getters
7 years ago
a66682374f
shader_ir: Add attribute getters
7 years ago
9d5d96500c
shader_ir: Add constant buffer getters
7 years ago
7f89f99c60
shader_ir: Add register getter
7 years ago
f43041efe1
shader_ir: Add immediate node constructors
7 years ago
25f868d8be
shader_ir: Initial implementation
7 years ago
a5b9cd4d18
Remove references to PICA and rasterizers in video_core
8 years ago
1089bdda80
Improved performance of FromAttributeBuffer
Ternary operator is optimized by the compiler
whereas std::min() is meant to return a value.
I've noticed a 5%-10% emulation speed increase.
8 years ago
6d51febdc4
pica/shader/jit: implement SETEMIT and EMIT
9 years ago
4283f4b244
correct constness
9 years ago
4d4dbc83a7
pica/shader/interpreter: implement SETEMIT and EMIT
9 years ago
2599928707
pica/shader: extend UnitState for GS
Among four shader units in pica, a special unit can be configured to run both VS and GS program. GSUnitState represents this unit, which extends UnitState (which represents the other three normal units) with extra state for primitive emitting. It uses lots of raw pointers to represent internal structure in order to keep it standard layout type for JIT to access.
This unit doesn't handle triangle winding (inverting) itself; instead, it calls a WindingSetter handler. This will be explained in the following commits
9 years ago
dc6f41bcc5
pica/shader_interpreter: fix off-by-one in LOOP
9 years ago
ccdeacf149
Stop using reserved operator names (and/or/xor) with Xbyak
Also has the Dynarmic upgrade with the same change
9 years ago
b9cc8596a2
Pica: Set program code / swizzle data limit to 4096
One of the later commits will enable writing to GS regs.
It turns out that on startup, most games will write 4096 GS program words.
The current limit of 1024 would hence result in 3072 (4096 - 1024) error messages:
```
HW.GPU <Error> video_core/shader/shader.cpp:WriteProgramCode:229: Invalid GS program offset 1024
```
New constants have been introduced to represent these limits.
The swizzle data size has also been raised. This matches the given field sizes of [GPUREG_SH_OPDESCS_INDEX](https://3dbrew.org/wiki/GPU/Internal_Registers#GPUREG_SH_OPDESCS_INDEX ) and [GPUREG_SH_CODETRANSFER_INDEX](https://www.3dbrew.org/wiki/GPU/Internal_Registers#GPUREG_SH_CODETRANSFER_INDEX ) (12 bit = [0; 4095]).
9 years ago
ReinUsesLisp