501284a81a
shader_decode: Implement BFE
7 years ago
e444a6553f
shader_decode: Implement FSET
7 years ago
3052eae25e
shader_decode: Implement F2I
7 years ago
8abe5ba2c8
shader_decode: Implement I2F
7 years ago
c849b5b320
shader_decode: Implement F2F
7 years ago
9118deb990
shader_decode: Stub DEPBAR
7 years ago
97f33f00cf
shader_decode: Implement SSY and SYNC
7 years ago
abdbafbc20
shader_decode: Implement PSETP
7 years ago
802c23b8a8
shader_decode: Implement TMML
7 years ago
2b90637f4b
shader_decode: Implement TEX and TXQ
7 years ago
878672f371
shader_decode: Implement TEXS (F32)
7 years ago
c703f0aee4
shader_decode: Implement FSETP
7 years ago
8215ae942c
shader_decode: Partially implement BRA
7 years ago
4f95dc950e
shader_decode: Implement IPA
7 years ago
cacb934f21
shader_decode: Implement EXIT
7 years ago
0c049e0a21
shader_decode: Implement ST_A
7 years ago
e3f1233ce1
shader_decode: Implement LD_A
7 years ago
ea358bd4bf
shader_decode: Implement FADD32I
7 years ago
c9b2a1b051
shader_decode: Implement FMUL32_IMM
7 years ago
2edee801ce
shader_decode: Implement MOV32_IMM
7 years ago
06cb910c6d
shader_decode: Stub RRO_C, RRO_R and RRO_IMM
7 years ago
5e6a0a08c1
shader_decode: Implement FMNMX_C, FMNMX_R and FMNMX_IMM
7 years ago
964ddeeb90
shader_decode: Implement MUFU
7 years ago
4ccaa1402d
shader_decode: Implement FADD_C, FADD_R and FADD_IMM
7 years ago
7c192ec43f
shader_decode: Implement FMUL_C, FMUL_R and FMUL_IMM
7 years ago
4c70d5b8eb
shader_decode: Implement MOV_C and MOV_R
7 years ago
0c6fb456e0
glsl_decompiler: Implementation
7 years ago
fbc67a0563
shader_ir: Add condition code helper
7 years ago
a58abbcfc4
shader_ir: Add predicate combiner helper
7 years ago
bf07272695
shader_ir: Add comparison helpers
7 years ago
60f044df56
shader_ir: Add half float helpers
7 years ago
e3c55e31d7
shader_ir: Add integer helpers
7 years ago
833d0806f9
shader_ir: Add float helpers
7 years ago
6b9eea3fe5
shader_ir: Add setters
7 years ago
12a95ff453
shader_ir: Add local memory getters
7 years ago
2f87fd060d
shader_ir: Add internal flag getters
7 years ago
15f431f0cb
shader_ir: Add attribute getters
7 years ago
864e8f55cf
shader_ir: Add constant buffer getters
7 years ago
5e639bfcf6
shader_ir: Add register getter
7 years ago
4aaa2192b9
shader_ir: Add immediate node constructors
7 years ago
15a0e1481d
shader_ir: Initial implementation
7 years ago
1d28b2e142
Remove references to PICA and rasterizers in video_core
8 years ago
a234e4c200
Improved performance of FromAttributeBuffer
Ternary operator is optimized by the compiler
whereas std::min() is meant to return a value.
I've noticed a 5%-10% emulation speed increase.
8 years ago
8285ca4ad8
pica/shader/jit: implement SETEMIT and EMIT
9 years ago
bb63ae3052
correct constness
9 years ago
28128348f2
pica/shader/interpreter: implement SETEMIT and EMIT
9 years ago
46c6973d2b
pica/shader: extend UnitState for GS
Among four shader units in pica, a special unit can be configured to run both VS and GS program. GSUnitState represents this unit, which extends UnitState (which represents the other three normal units) with extra state for primitive emitting. It uses lots of raw pointers to represent internal structure in order to keep it standard layout type for JIT to access.
This unit doesn't handle triangle winding (inverting) itself; instead, it calls a WindingSetter handler. This will be explained in the following commits
9 years ago
c89f804a01
pica/shader_interpreter: fix off-by-one in LOOP
9 years ago
f6715f98f5
Stop using reserved operator names (and/or/xor) with Xbyak
Also has the Dynarmic upgrade with the same change
9 years ago
925724c990
Pica: Set program code / swizzle data limit to 4096
One of the later commits will enable writing to GS regs.
It turns out that on startup, most games will write 4096 GS program words.
The current limit of 1024 would hence result in 3072 (4096 - 1024) error messages:
```
HW.GPU <Error> video_core/shader/shader.cpp:WriteProgramCode:229: Invalid GS program offset 1024
```
New constants have been introduced to represent these limits.
The swizzle data size has also been raised. This matches the given field sizes of [GPUREG_SH_OPDESCS_INDEX](https://3dbrew.org/wiki/GPU/Internal_Registers#GPUREG_SH_OPDESCS_INDEX ) and [GPUREG_SH_CODETRANSFER_INDEX](https://www.3dbrew.org/wiki/GPU/Internal_Registers#GPUREG_SH_CODETRANSFER_INDEX ) (12 bit = [0; 4095]).
9 years ago
ReinUsesLisp