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@ -175,6 +175,43 @@ Node ShaderIR::GetOperandAbsNegInteger(Node value, bool absolute, bool negate, b |
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return value; |
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} |
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Node ShaderIR::UnpackHalfImmediate(Instruction instr, bool has_negation) { |
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const Node value = Immediate(instr.half_imm.PackImmediates()); |
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if (!has_negation) { |
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return value; |
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} |
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const Node first_negate = GetPredicate(instr.half_imm.first_negate != 0); |
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const Node second_negate = GetPredicate(instr.half_imm.second_negate != 0); |
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return Operation(OperationCode::HNegate, HALF_NO_PRECISE, value, first_negate, second_negate); |
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} |
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Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) { |
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switch (merge) { |
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case Tegra::Shader::HalfMerge::H0_H1: |
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return src; |
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case Tegra::Shader::HalfMerge::F32: |
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return Operation(OperationCode::HMergeF32, src); |
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case Tegra::Shader::HalfMerge::Mrg_H0: |
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return Operation(OperationCode::HMergeH0, dest, src); |
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case Tegra::Shader::HalfMerge::Mrg_H1: |
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return Operation(OperationCode::HMergeH1, dest, src); |
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} |
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UNREACHABLE(); |
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return src; |
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} |
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Node ShaderIR::GetOperandAbsNegHalf(Node value, bool absolute, bool negate) { |
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if (absolute) { |
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value = Operation(OperationCode::HAbsolute, HALF_NO_PRECISE, value); |
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} |
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if (negate) { |
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value = Operation(OperationCode::HNegate, HALF_NO_PRECISE, value, GetPredicate(true), |
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GetPredicate(true)); |
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} |
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return value; |
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} |
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void ShaderIR::SetRegister(BasicBlock& bb, Register dest, Node src) { |
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bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src)); |
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} |
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