FernandoS27
5 years ago
committed by
ameerj
ameerj
21 changed files with 437 additions and 48 deletions
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4src/shader_recompiler/CMakeLists.txt
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3src/shader_recompiler/backend/spirv/emit_spirv.h
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10src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
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4src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
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2src/shader_recompiler/environment.h
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12src/shader_recompiler/frontend/ir/ir_emitter.cpp
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4src/shader_recompiler/frontend/ir/ir_emitter.h
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1src/shader_recompiler/frontend/ir/microinstruction.cpp
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3src/shader_recompiler/frontend/ir/opcodes.inc
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58src/shader_recompiler/frontend/maxwell/control_flow.cpp
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7src/shader_recompiler/frontend/maxwell/control_flow.h
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108src/shader_recompiler/frontend/maxwell/indirect_branch_table_track.cpp
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28src/shader_recompiler/frontend/maxwell/indirect_branch_table_track.h
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1src/shader_recompiler/frontend/maxwell/instruction.h
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57src/shader_recompiler/frontend/maxwell/structured_control_flow.cpp
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36src/shader_recompiler/frontend/maxwell/translate/impl/branch_indirect.cpp
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29src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
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39src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.h
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8src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
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21src/shader_recompiler/ir_opt/ssa_rewrite_pass.cpp
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50src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <optional>
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/decode.h"
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#include "shader_recompiler/frontend/maxwell/indirect_branch_table_track.h"
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#include "shader_recompiler/frontend/maxwell/opcodes.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/load_constant.h"
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namespace Shader::Maxwell { |
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namespace { |
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union Encoding { |
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u64 raw; |
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BitField<0, 8, IR::Reg> dest_reg; |
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BitField<8, 8, IR::Reg> src_reg; |
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BitField<20, 19, u64> immediate; |
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BitField<56, 1, u64> is_negative; |
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BitField<20, 24, s64> brx_offset; |
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}; |
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template <typename Callable> |
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std::optional<u64> Track(Environment& env, Location block_begin, Location& pos, Callable&& func) { |
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while (pos >= block_begin) { |
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const u64 insn{env.ReadInstruction(pos.Offset())}; |
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--pos; |
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if (func(insn, Decode(insn))) { |
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return insn; |
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} |
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} |
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return std::nullopt; |
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} |
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std::optional<u64> TrackLDC(Environment& env, Location block_begin, Location& pos, |
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IR::Reg brx_reg) { |
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return Track(env, block_begin, pos, [brx_reg](u64 insn, Opcode opcode) { |
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const LDC::Encoding ldc{insn}; |
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return opcode == Opcode::LDC && ldc.dest_reg == brx_reg && ldc.size == LDC::Size::B32 && |
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ldc.mode == LDC::Mode::Default; |
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}); |
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} |
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std::optional<u64> TrackSHL(Environment& env, Location block_begin, Location& pos, |
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IR::Reg ldc_reg) { |
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return Track(env, block_begin, pos, [ldc_reg](u64 insn, Opcode opcode) { |
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const Encoding shl{insn}; |
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return opcode == Opcode::SHL_imm && shl.dest_reg == ldc_reg; |
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}); |
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} |
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std::optional<u64> TrackIMNMX(Environment& env, Location block_begin, Location& pos, |
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IR::Reg shl_reg) { |
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return Track(env, block_begin, pos, [shl_reg](u64 insn, Opcode opcode) { |
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const Encoding imnmx{insn}; |
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return opcode == Opcode::IMNMX_imm && imnmx.dest_reg == shl_reg; |
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}); |
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} |
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} // Anonymous namespace
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std::optional<IndirectBranchTableInfo> TrackIndirectBranchTable(Environment& env, Location brx_pos, |
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Location block_begin) { |
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const u64 brx_insn{env.ReadInstruction(brx_pos.Offset())}; |
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const Opcode brx_opcode{Decode(brx_insn)}; |
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if (brx_opcode != Opcode::BRX && brx_opcode != Opcode::JMX) { |
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throw LogicError("Tracked instruction is not BRX or JMX"); |
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} |
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const IR::Reg brx_reg{Encoding{brx_insn}.src_reg}; |
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const s32 brx_offset{static_cast<s32>(Encoding{brx_insn}.brx_offset)}; |
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Location pos{brx_pos}; |
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const std::optional<u64> ldc_insn{TrackLDC(env, block_begin, pos, brx_reg)}; |
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if (!ldc_insn) { |
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return std::nullopt; |
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} |
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const LDC::Encoding ldc{*ldc_insn}; |
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const u32 cbuf_index{static_cast<u32>(ldc.index)}; |
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const u32 cbuf_offset{static_cast<u32>(static_cast<s32>(ldc.offset.Value()))}; |
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const IR::Reg ldc_reg{ldc.src_reg}; |
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const std::optional<u64> shl_insn{TrackSHL(env, block_begin, pos, ldc_reg)}; |
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if (!shl_insn) { |
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return std::nullopt; |
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} |
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const Encoding shl{*shl_insn}; |
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const IR::Reg shl_reg{shl.src_reg}; |
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const std::optional<u64> imnmx_insn{TrackIMNMX(env, block_begin, pos, shl_reg)}; |
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if (!imnmx_insn) { |
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return std::nullopt; |
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} |
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const Encoding imnmx{*imnmx_insn}; |
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if (imnmx.is_negative != 0) { |
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return std::nullopt; |
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} |
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const u32 imnmx_immediate{static_cast<u32>(imnmx.immediate.Value())}; |
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return IndirectBranchTableInfo{ |
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.cbuf_index{cbuf_index}, |
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.cbuf_offset{cbuf_offset}, |
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.num_entries{imnmx_immediate + 1}, |
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.branch_offset{brx_offset}, |
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.branch_reg{brx_reg}, |
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}; |
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} |
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} // namespace Shader::Maxwell
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// Copyright 2021 yuzu Emulator Project |
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// Licensed under GPLv2 or any later version |
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// Refer to the license.txt file included. |
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#pragma once |
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#include <optional> |
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#include "common/bit_field.h" |
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#include "common/common_types.h" |
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#include "shader_recompiler/environment.h" |
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#include "shader_recompiler/frontend/ir/reg.h" |
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#include "shader_recompiler/frontend/maxwell/location.h" |
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namespace Shader::Maxwell { |
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struct IndirectBranchTableInfo { |
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u32 cbuf_index{}; |
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u32 cbuf_offset{}; |
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u32 num_entries{}; |
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s32 branch_offset{}; |
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IR::Reg branch_reg{}; |
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}; |
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std::optional<IndirectBranchTableInfo> TrackIndirectBranchTable(Environment& env, Location brx_pos, |
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Location block_begin); |
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} // namespace Shader::Maxwell |
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@ -0,0 +1,36 @@ |
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell { |
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namespace { |
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void Check(u64 insn) { |
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union { |
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u64 raw; |
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BitField<5, 1, u64> cbuf_mode; |
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BitField<6, 1, u64> lmt; |
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} const encoding{insn}; |
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if (encoding.cbuf_mode != 0) { |
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throw NotImplementedException("Constant buffer mode"); |
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} |
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if (encoding.lmt != 0) { |
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throw NotImplementedException("LMT"); |
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} |
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} |
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} // Anonymous namespace
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void TranslatorVisitor::BRX(u64 insn) { |
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Check(insn); |
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} |
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void TranslatorVisitor::JMX(u64 insn) { |
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Check(insn); |
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} |
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} // namespace Shader::Maxwell
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// Copyright 2021 yuzu Emulator Project |
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// Licensed under GPLv2 or any later version |
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// Refer to the license.txt file included. |
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#pragma once |
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#include "common/bit_field.h" |
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#include "common/common_types.h" |
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#include "shader_recompiler/frontend/ir/reg.h" |
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namespace Shader::Maxwell::LDC { |
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enum class Mode : u64 { |
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Default, |
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IL, |
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IS, |
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ISL, |
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}; |
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enum class Size : u64 { |
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U8, |
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S8, |
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U16, |
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S16, |
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B32, |
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B64, |
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}; |
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union Encoding { |
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u64 raw; |
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BitField<0, 8, IR::Reg> dest_reg; |
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BitField<8, 8, IR::Reg> src_reg; |
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BitField<20, 16, s64> offset; |
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BitField<36, 5, u64> index; |
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BitField<44, 2, Mode> mode; |
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BitField<48, 3, Size> size; |
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}; |
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} // namespace Shader::Maxwell::LDC |
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