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@ -4,43 +4,6 @@ |
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#pragma once |
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#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) |
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#define BIT(n) ((instr >> (n)) & 1) |
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// For MUL instructions |
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#define RDHi ((instr >> 16) & 0xF) |
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#define RDLo ((instr >> 12) & 0xF) |
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#define MUL_RD ((instr >> 16) & 0xF) |
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#define MUL_RN ((instr >> 12) & 0xF) |
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#define RS ((instr >> 8) & 0xF) |
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#define RD ((instr >> 12) & 0xF) |
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#define RN ((instr >> 16) & 0xF) |
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#define RM (instr & 0xF) |
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// CP15 registers |
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#define OPCODE_1 BITS(21, 23) |
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#define CRn BITS(16, 19) |
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#define CRm BITS(0, 3) |
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#define OPCODE_2 BITS(5, 7) |
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#define I BIT(25) |
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#define S BIT(20) |
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#define SHIFT BITS(5,6) |
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#define SHIFT_IMM BITS(7,11) |
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#define IMMH BITS(8,11) |
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#define IMML BITS(0,3) |
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#define LSPBIT BIT(24) |
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#define LSUBIT BIT(23) |
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#define LSBBIT BIT(22) |
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#define LSWBIT BIT(21) |
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#define LSLBIT BIT(20) |
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#define LSSHBITS BITS(5,6) |
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#define OFFSET12 BITS(0,11) |
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#define SBIT BIT(20) |
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#define DESTReg (BITS (12, 15)) |
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int decode_arm_instr(uint32_t instr, int32_t *idx); |
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enum DECODE_STATUS { |
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