assert_msg -> assert

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp

@@ -28,7 +28,7 @@ AddressSpace::AddressSpace(size_t code_cache_size)
         , mem(code_cache_size)
         , code(mem.ptr(), mem.ptr())
         , fastmem_manager(exception_handler) {
-    ASSERT_MSG(code_cache_size <= 128 * 1024 * 1024, "code_cache_size > 128 MiB not currently supported");
+    ASSERT(code_cache_size <= 128 * 1024 * 1024 && "code_cache_size > 128 MiB not currently supported");
 
     exception_handler.Register(mem, code_cache_size);
     exception_handler.SetFastmemCallback([this](u64 host_pc) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp

@@ -956,7 +956,7 @@ void EmitIR<IR::Opcode::VectorMultiply32>(oaknut::CodeGenerator& code, EmitConte
 
 template<>
 void EmitIR<IR::Opcode::VectorMultiply64>(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst) {
-    ASSERT_MSG(ctx.conf.very_verbose_debugging_output, "VectorMultiply64 is for debugging only");
+    ASSERT(ctx.conf.very_verbose_debugging_output && "VectorMultiply64 is for debugging only");
     EmitThreeOp(code, ctx, inst, [&](auto& Qresult, auto& Qa, auto& Qb) {
         code.FMOV(Xscratch0, Qa->toD());
         code.FMOV(Xscratch1, Qb->toD());
@@ -1600,7 +1600,7 @@ void EmitIR<IR::Opcode::VectorSub64>(oaknut::CodeGenerator& code, EmitContext& c
 template<>
 void EmitIR<IR::Opcode::VectorTable>(oaknut::CodeGenerator&, EmitContext&, IR::Inst* inst) {
     // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    ASSERT_MSG(inst->UseCount() == 1, "Table cannot be used multiple times");
+    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }
 
 template<>

src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp

@@ -136,7 +136,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT_MSG(ValueLocation(arg.GetInst()), "argument must already been defined");
+            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -508,7 +508,7 @@ void RegAlloc::SpillFlags() {
 
 int RegAlloc::FindFreeSpill() const {
     const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    ASSERT_MSG(iter != spills.end(), "All spill locations are full");
+    ASSERT(iter != spills.end() && "All spill locations are full");
     return static_cast<int>(iter - spills.begin());
 }
 

src/dynarmic/src/dynarmic/backend/exception_handler_macos.cpp

@@ -88,7 +88,7 @@ private:
 };
 
 MachHandler::MachHandler() {
-#define KCHECK(x) ASSERT_MSG((x) == KERN_SUCCESS, "dynarmic: macOS MachHandler: init failure at {}", #x)
+#define KCHECK(x) ASSERT((x) == KERN_SUCCESS && "dynarmic: macOS MachHandler: init failure at {}", #x)
 
     KCHECK(mach_port_allocate(mach_task_self(), MACH_PORT_RIGHT_RECEIVE, &server_port));
     KCHECK(mach_port_insert_right(mach_task_self(), server_port, server_port, MACH_MSG_TYPE_MAKE_SEND));

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp

@@ -105,7 +105,7 @@ void EmitA32Cond(biscuit::Assembler& as, EmitContext&, IR::Cond cond, biscuit::L
         as.BNEZ(Xscratch0, label);
         break;
     default:
-        ASSERT_MSG(false, "Unknown cond {}", static_cast<size_t>(cond));
+        ASSERT(false && "Unknown cond {}", static_cast<size_t>(cond));
         break;
     }
 }

src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp

@@ -105,7 +105,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(IR::Inst* inst) {
         const IR::Value arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT_MSG(ValueLocation(arg.GetInst()), "argument must already been defined");
+            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
             ValueInfo(arg.GetInst()).uses_this_inst++;
         }
     }
@@ -299,7 +299,7 @@ void RegAlloc::SpillFpr(u32 index) {
 
 u32 RegAlloc::FindFreeSpill() const {
     const auto iter = std::find_if(spills.begin(), spills.end(), [](const HostLocInfo& info) { return info.values.empty(); });
-    ASSERT_MSG(iter != spills.end(), "All spill locations are full");
+    ASSERT(iter != spills.end() && "All spill locations are full");
     return static_cast<u32>(iter - spills.begin());
 }
 

src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp

@@ -1126,9 +1126,9 @@ std::string A32EmitX64::LocationDescriptorToFriendlyName(const IR::LocationDescr
 }
 
 void A32EmitX64::EmitTerminalImpl(IR::Term::Interpret terminal, IR::LocationDescriptor initial_location, bool) {
-    ASSERT_MSG(A32::LocationDescriptor{terminal.next}.TFlag() == A32::LocationDescriptor{initial_location}.TFlag(), "Unimplemented");
-    ASSERT_MSG(A32::LocationDescriptor{terminal.next}.EFlag() == A32::LocationDescriptor{initial_location}.EFlag(), "Unimplemented");
-    ASSERT_MSG(terminal.num_instructions == 1, "Unimplemented");
+    ASSERT(A32::LocationDescriptor{terminal.next}.TFlag() == A32::LocationDescriptor{initial_location}.TFlag() && "Unimplemented");
+    ASSERT(A32::LocationDescriptor{terminal.next}.EFlag() == A32::LocationDescriptor{initial_location}.EFlag() && "Unimplemented");
+    ASSERT(terminal.num_instructions == 1 && "Unimplemented");
 
     code.mov(code.ABI_PARAM2.cvt32(), A32::LocationDescriptor{terminal.next}.PC());
     code.mov(code.ABI_PARAM3.cvt32(), 1);

src/dynarmic/src/dynarmic/backend/x64/a64_emit_x64.cpp

@@ -130,7 +130,7 @@ A64EmitX64::BlockDescriptor A64EmitX64::Emit(IR::Block& block) noexcept {
 #undef A32OPC
 #undef A64OPC
         default: [[unlikely]] {
-                ASSERT_MSG(false, "Invalid opcode: {:x}", std::size_t(opcode));
+                ASSERT(false && "Invalid opcode: {:x}", std::size_t(opcode));
             goto finish_this_inst;
         }
         }

src/dynarmic/src/dynarmic/backend/x64/block_of_code.cpp

@@ -507,7 +507,7 @@ void BlockOfCode::LoadRequiredFlagsForCondFromRax(IR::Cond cond) {
     case IR::Cond::NV:
         break;
     default:
-        ASSERT_MSG(false, "Unknown cond {}", static_cast<size_t>(cond));
+        ASSERT(false && "Unknown cond {}", static_cast<size_t>(cond));
         break;
     }
 }

src/dynarmic/src/dynarmic/backend/x64/emit_x64.cpp

@@ -59,7 +59,7 @@ std::optional<EmitX64::BlockDescriptor> EmitX64::GetBasicBlock(IR::LocationDescr
 }
 
 void EmitX64::EmitInvalid(EmitContext&, IR::Inst* inst) {
-    ASSERT_MSG(false, "Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
+    ASSERT(false && "Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
 }
 
 void EmitX64::EmitVoid(EmitContext&, IR::Inst*) {
@@ -352,7 +352,7 @@ void EmitX64::EmitTerminal(IR::Terminal terminal, IR::LocationDescriptor initial
         if constexpr (!std::is_same_v<T, IR::Term::Invalid>) {
             this->EmitTerminalImpl(x, initial_location, is_single_step);
         } else {
-            ASSERT_MSG(false, "Invalid terminal");
+            ASSERT(false && "Invalid terminal");
         }
     }, terminal);
 }

src/dynarmic/src/dynarmic/backend/x64/emit_x64_data_processing.cpp

@@ -195,7 +195,7 @@ static void EmitConditionalSelect(BlockOfCode& code, EmitContext& ctx, IR::Inst*
         code.mov(else_, then_);
         break;
     default:
-        ASSERT_MSG(false, "Invalid cond {}", static_cast<size_t>(args[0].GetImmediateCond()));
+        ASSERT(false && "Invalid cond {}", static_cast<size_t>(args[0].GetImmediateCond()));
     }
 
     ctx.reg_alloc.DefineValue(inst, else_);

src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp

@@ -5039,7 +5039,7 @@ void EmitX64::EmitVectorSub64(EmitContext& ctx, IR::Inst* inst) {
 
 void EmitX64::EmitVectorTable(EmitContext&, IR::Inst* inst) {
     // Do nothing. We *want* to hold on to the refcount for our arguments, so VectorTableLookup can use our arguments.
-    ASSERT_MSG(inst->UseCount() == 1, "Table cannot be used multiple times");
+    ASSERT(inst->UseCount() == 1 && "Table cannot be used multiple times");
 }
 
 void EmitX64::EmitVectorTableLookup64(EmitContext& ctx, IR::Inst* inst) {

src/dynarmic/src/dynarmic/backend/x64/oparg.h

@@ -56,7 +56,7 @@ struct OpArg {
                 inner_reg = inner_reg.cvt64();
                 return;
             default:
-                ASSERT_MSG(false, "Invalid bits");
+                ASSERT(false && "Invalid bits");
                 return;
             }
         }

src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp

@@ -223,7 +223,7 @@ RegAlloc::ArgumentInfo RegAlloc::GetArgumentInfo(const IR::Inst* inst) noexcept
         const auto arg = inst->GetArg(i);
         ret[i].value = arg;
         if (!arg.IsImmediate() && !IsValuelessType(arg.GetType())) {
-            ASSERT_MSG(ValueLocation(arg.GetInst()), "argument must already been defined");
+            ASSERT(ValueLocation(arg.GetInst()) && "argument must already been defined");
             LocInfo(*ValueLocation(arg.GetInst())).AddArgReference();
         }
     }
@@ -467,19 +467,19 @@ HostLoc RegAlloc::SelectARegister(const boost::container::static_vector<HostLoc,
     auto const it_final = it_empty_candidate != desired_locations.cend()
         ? it_empty_candidate : it_candidate != desired_locations.cend()
         ? it_candidate : it_rex_candidate;
-    ASSERT_MSG(it_final != desired_locations.cend(), "All candidate registers have already been allocated");
+    ASSERT(it_final != desired_locations.cend() && "All candidate registers have already been allocated");
     // Evil magic - increment LRU counter (will wrap at 256)
     const_cast<RegAlloc*>(this)->LocInfo(*it_final).lru_counter++;
     return *it_final;
 }
 
 void RegAlloc::DefineValueImpl(IR::Inst* def_inst, HostLoc host_loc) noexcept {
-    ASSERT_MSG(!ValueLocation(def_inst), "def_inst has already been defined");
+    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
     LocInfo(host_loc).AddValue(def_inst);
 }
 
 void RegAlloc::DefineValueImpl(IR::Inst* def_inst, const IR::Value& use_inst) noexcept {
-    ASSERT_MSG(!ValueLocation(def_inst), "def_inst has already been defined");
+    ASSERT(!ValueLocation(def_inst) && "def_inst has already been defined");
 
     if (use_inst.IsImmediate()) {
         const HostLoc location = ScratchImpl(gpr_order);
@@ -488,13 +488,13 @@ void RegAlloc::DefineValueImpl(IR::Inst* def_inst, const IR::Value& use_inst) no
         return;
     }
 
-    ASSERT_MSG(ValueLocation(use_inst.GetInst()), "use_inst must already be defined");
+    ASSERT(ValueLocation(use_inst.GetInst()) && "use_inst must already be defined");
     const HostLoc location = *ValueLocation(use_inst.GetInst());
     DefineValueImpl(def_inst, location);
 }
 
 HostLoc RegAlloc::LoadImmediate(IR::Value imm, HostLoc host_loc) noexcept {
-    ASSERT_MSG(imm.IsImmediate(), "imm is not an immediate");
+    ASSERT(imm.IsImmediate() && "imm is not an immediate");
     if (HostLocIsGPR(host_loc)) {
         const Xbyak::Reg64 reg = HostLocToReg64(host_loc);
         const u64 imm_value = imm.GetImmediateAsU64();
@@ -521,7 +521,7 @@ void RegAlloc::Move(HostLoc to, HostLoc from) noexcept {
     const size_t bit_width = LocInfo(from).GetMaxBitWidth();
     ASSERT(LocInfo(to).IsEmpty() && !LocInfo(from).IsLocked());
     ASSERT(bit_width <= HostLocBitWidth(to));
-    ASSERT_MSG(!LocInfo(from).IsEmpty(), "Mov eliminated");
+    ASSERT(!LocInfo(from).IsEmpty() && "Mov eliminated");
     EmitMove(bit_width, to, from);
     LocInfo(to) = std::exchange(LocInfo(from), {});
 }
@@ -554,9 +554,9 @@ void RegAlloc::MoveOutOfTheWay(HostLoc reg) noexcept {
 }
 
 void RegAlloc::SpillRegister(HostLoc loc) noexcept {
-    ASSERT_MSG(HostLocIsRegister(loc), "Only registers can be spilled");
-    ASSERT_MSG(!LocInfo(loc).IsEmpty(), "There is no need to spill unoccupied registers");
-    ASSERT_MSG(!LocInfo(loc).IsLocked(), "Registers that have been allocated must not be spilt");
+    ASSERT(HostLocIsRegister(loc) && "Only registers can be spilled");
+    ASSERT(!LocInfo(loc).IsEmpty() && "There is no need to spill unoccupied registers");
+    ASSERT(!LocInfo(loc).IsLocked() && "Registers that have been allocated must not be spilt");
     auto const new_loc = FindFreeSpill(HostLocIsXMM(loc));
     Move(new_loc, loc);
 }
@@ -589,7 +589,7 @@ void RegAlloc::EmitMove(const size_t bit_width, const HostLoc to, const HostLoc
     auto const spill_to_op_arg_helper = [&](HostLoc loc, size_t reserved_stack_space) {
         ASSERT(HostLocIsSpill(loc));
         size_t i = size_t(loc) - size_t(HostLoc::FirstSpill);
-        ASSERT_MSG(i < SpillCount, "Spill index greater than number of available spill locations");
+        ASSERT(i < SpillCount && "Spill index greater than number of available spill locations");
         return Xbyak::util::rsp + reserved_stack_space + ABI_SHADOW_SPACE + offsetof(StackLayout, spill) + i * sizeof(StackLayout::spill[0]);
     };
     auto const spill_xmm_to_op = [&](const HostLoc loc) {

src/dynarmic/src/dynarmic/common/assert.h

@@ -31,10 +31,10 @@ template<typename... Ts>
 #endif
 
 #ifndef ASSERT
-#define ASSERT(_a_) ASSERT_MSG(_a_, "")
+#define ASSERT(_a_) ASSERT(_a_ && "")
 #endif
 #ifndef UNREACHABLE
-#define UNREACHABLE() ASSERT_MSG(false, "unreachable")
+#define UNREACHABLE() ASSERT(false && "unreachable")
 #endif
 #ifdef _DEBUG
 #ifndef DEBUG_ASSERT

src/dynarmic/src/dynarmic/common/fp/fpcr.h

@@ -73,7 +73,7 @@ public:
 
     /// Set rounding mode control field.
     void RMode(FP::RoundingMode rounding_mode) {
-        ASSERT_MSG(static_cast<u32>(rounding_mode) <= 0b11, "FPCR: Invalid rounding mode");
+        ASSERT(static_cast<u32>(rounding_mode) <= 0b11 && "FPCR: Invalid rounding mode");
         value = mcl::bit::set_bits<22, 23>(value, static_cast<u32>(rounding_mode));
     }
 
@@ -93,7 +93,7 @@ public:
     /// Set the stride of a vector when executing AArch32 VFP instructions.
     /// This field has no function in AArch64 state.
     void Stride(size_t stride) {
-        ASSERT_MSG(stride >= 1 && stride <= 2, "FPCR: Invalid stride");
+        ASSERT(stride >= 1 && stride <= 2 && "FPCR: Invalid stride");
         value = mcl::bit::set_bits<20, 21>(value, stride == 1 ? 0b00u : 0b11u);
     }
 
@@ -116,7 +116,7 @@ public:
     /// Sets the length of a vector when executing AArch32 VFP instructions.
     /// This field has no function in AArch64 state.
     void Len(size_t len) {
-        ASSERT_MSG(len >= 1 && len <= 8, "FPCR: Invalid len");
+        ASSERT(len >= 1 && len <= 8 && "FPCR: Invalid len");
         value = mcl::bit::set_bits<16, 18>(value, static_cast<u32>(len - 1));
     }
 

src/dynarmic/src/dynarmic/frontend/A32/translate/conditional_state.cpp

@@ -21,7 +21,7 @@
 namespace Dynarmic::A32 {
 
 bool CondCanContinue(const ConditionalState cond_state, const A32::IREmitter& ir) {
-    ASSERT_MSG(cond_state != ConditionalState::Break, "Should never happen.");
+    ASSERT(cond_state != ConditionalState::Break && "Should never happen.");
     if (cond_state == ConditionalState::None)
         return true;
 

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/load_store.cpp

@@ -93,7 +93,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re
         return UnpredictableInstruction();
     }
 
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -124,7 +124,7 @@ bool TranslatorVisitor::arm_LDR_imm(Cond cond, bool P, bool U, bool W, Reg n, Re
 // LDR <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDR <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDR_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if (m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -182,7 +182,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R
         return UnpredictableInstruction();
     }
 
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -207,7 +207,7 @@ bool TranslatorVisitor::arm_LDRB_imm(Cond cond, bool P, bool U, bool W, Reg n, R
 // LDRB <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRB <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Imm<5> imm5, ShiftType shift, Reg m) {
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -350,7 +350,7 @@ bool TranslatorVisitor::arm_LDRD_reg(Cond cond, bool P, bool U, bool W, Reg n, R
 
 // LDRH <Rt>, [PC, #-/+<imm>]
 bool TranslatorVisitor::arm_LDRH_lit(Cond cond, bool P, bool U, bool W, Reg t, Imm<4> imm8a, Imm<4> imm8b) {
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if (P == W) {
         return UnpredictableInstruction();
     }
@@ -380,7 +380,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R
         return UnpredictableInstruction();
     }
 
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -405,7 +405,7 @@ bool TranslatorVisitor::arm_LDRH_imm(Cond cond, bool P, bool U, bool W, Reg n, R
 // LDRH <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRH <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -454,7 +454,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n,
         return UnpredictableInstruction();
     }
 
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -479,7 +479,7 @@ bool TranslatorVisitor::arm_LDRSB_imm(Cond cond, bool P, bool U, bool W, Reg n,
 // LDRSB <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRSB <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRSB_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -527,7 +527,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n,
         return UnpredictableInstruction();
     }
 
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if ((!P || W) && n == t) {
         return UnpredictableInstruction();
     }
@@ -552,7 +552,7 @@ bool TranslatorVisitor::arm_LDRSH_imm(Cond cond, bool P, bool U, bool W, Reg n,
 // LDRSH <Rt>, [<Rn>, #+/-<Rm>]{!}
 // LDRSH <Rt>, [<Rn>], #+/-<Rm>
 bool TranslatorVisitor::arm_LDRSH_reg(Cond cond, bool P, bool U, bool W, Reg n, Reg t, Reg m) {
-    ASSERT_MSG(!(!P && W), "T form of instruction unimplemented");
+    ASSERT(!(!P && W) && "T form of instruction unimplemented");
     if (t == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
     }

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/status_register_access.cpp

@@ -31,7 +31,7 @@ bool TranslatorVisitor::arm_MRS(Cond cond, Reg d) {
 
 // MSR<c> <spec_reg>, #<const>
 bool TranslatorVisitor::arm_MSR_imm(Cond cond, unsigned mask, int rotate, Imm<8> imm8) {
-    ASSERT_MSG(mask != 0, "Decode error");
+    ASSERT(mask != 0 && "Decode error");
 
     if (!ArmConditionPassed(cond)) {
         return true;

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb16.cpp

@@ -684,7 +684,7 @@ bool TranslatorVisitor::thumb16_NOP() {
 
 // IT{<x>{<y>{<z>}}} <cond>
 bool TranslatorVisitor::thumb16_IT(Imm<8> imm8) {
-    ASSERT_MSG((imm8.Bits<0, 3>() != 0b0000), "Decode Error");
+    ASSERT((imm8.Bits<0, 3>() != 0b0000) && "Decode Error");
     if (imm8.Bits<4, 7>() == 0b1111 || (imm8.Bits<4, 7>() == 0b1110 && mcl::bit::count_ones(imm8.Bits<0, 3>()) != 1)) {
         return UnpredictableInstruction();
     }

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_modified_immediate.cpp

@@ -20,7 +20,7 @@ bool TranslatorVisitor::thumb32_TST_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_AND_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -66,7 +66,7 @@ bool TranslatorVisitor::thumb32_MOV_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im
 }
 
 bool TranslatorVisitor::thumb32_ORR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT_MSG(n != Reg::PC, "Decode error");
+    ASSERT(n != Reg::PC && "Decode error");
     if (d == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -97,7 +97,7 @@ bool TranslatorVisitor::thumb32_MVN_imm(Imm<1> i, bool S, Imm<3> imm3, Reg d, Im
 }
 
 bool TranslatorVisitor::thumb32_ORN_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT_MSG(n != Reg::PC, "Decode error");
+    ASSERT(n != Reg::PC && "Decode error");
     if (d == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -125,7 +125,7 @@ bool TranslatorVisitor::thumb32_TEQ_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_EOR_imm(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -153,7 +153,7 @@ bool TranslatorVisitor::thumb32_CMN_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_ADD_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }
@@ -211,7 +211,7 @@ bool TranslatorVisitor::thumb32_CMP_imm(Imm<1> i, Reg n, Imm<3> imm3, Imm<8> imm
 }
 
 bool TranslatorVisitor::thumb32_SUB_imm_1(Imm<1> i, bool S, Reg n, Imm<3> imm3, Reg d, Imm<8> imm8) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
     if ((d == Reg::PC && !S) || n == Reg::PC) {
         return UnpredictableInstruction();
     }

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_plain_binary_immediate.cpp

@@ -17,7 +17,7 @@ namespace Dynarmic::A32 {
 using SaturationFunction = IR::ResultAndOverflow<IR::U32> (IREmitter::*)(const IR::U32&, size_t);
 
 static bool Saturation(TranslatorVisitor& v, bool sh, Reg n, Reg d, Imm<5> shift_amount, size_t saturate_to, SaturationFunction sat_fn) {
-    ASSERT_MSG(!(sh && shift_amount == 0), "Invalid decode");
+    ASSERT(!(sh && shift_amount == 0) && "Invalid decode");
 
     if (d == Reg::PC || n == Reg::PC) {
         return v.UnpredictableInstruction();

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/thumb32_data_processing_shifted_register.cpp

@@ -20,7 +20,7 @@ bool TranslatorVisitor::thumb32_TST_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_AND_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -64,7 +64,7 @@ bool TranslatorVisitor::thumb32_MOV_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2,
 }
 
 bool TranslatorVisitor::thumb32_ORR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT_MSG(n != Reg::PC, "Decode error");
+    ASSERT(n != Reg::PC && "Decode error");
 
     if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -94,7 +94,7 @@ bool TranslatorVisitor::thumb32_MVN_reg(bool S, Imm<3> imm3, Reg d, Imm<2> imm2,
 }
 
 bool TranslatorVisitor::thumb32_ORN_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT_MSG(n != Reg::PC, "Decode error");
+    ASSERT(n != Reg::PC && "Decode error");
 
     if (d == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -122,7 +122,7 @@ bool TranslatorVisitor::thumb32_TEQ_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_EOR_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -165,7 +165,7 @@ bool TranslatorVisitor::thumb32_CMN_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_ADD_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();
@@ -221,7 +221,7 @@ bool TranslatorVisitor::thumb32_CMP_reg(Reg n, Imm<3> imm3, Imm<2> imm2, ShiftTy
 }
 
 bool TranslatorVisitor::thumb32_SUB_reg(bool S, Reg n, Imm<3> imm3, Reg d, Imm<2> imm2, ShiftType type, Reg m) {
-    ASSERT_MSG(!(d == Reg::PC && S), "Decode error");
+    ASSERT(!(d == Reg::PC && S) && "Decode error");
 
     if ((d == Reg::PC && !S) || n == Reg::PC || m == Reg::PC) {
         return UnpredictableInstruction();

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/vfp.cpp

@@ -1301,11 +1301,11 @@ bool TranslatorVisitor::vfp_VSTR(Cond cond, bool U, bool D, Reg n, size_t Vd, bo
 // VSTM{mode}<c> <Rn>{!}, <list of double registers>
 bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p == u && w) {
@@ -1353,11 +1353,11 @@ bool TranslatorVisitor::vfp_VSTM_a1(Cond cond, bool p, bool u, bool D, bool w, R
 // VSTM{mode}<c> <Rn>{!}, <list of single registers>
 bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p == u && w) {
@@ -1396,11 +1396,11 @@ bool TranslatorVisitor::vfp_VSTM_a2(Cond cond, bool p, bool u, bool D, bool w, R
 // VLDM{mode}<c> <Rn>{!}, <list of double registers>
 bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p == u && w) {
@@ -1446,11 +1446,11 @@ bool TranslatorVisitor::vfp_VLDM_a1(Cond cond, bool p, bool u, bool D, bool w, R
 // VLDM{mode}<c> <Rn>{!}, <list of single registers>
 bool TranslatorVisitor::vfp_VLDM_a2(Cond cond, bool p, bool u, bool D, bool w, Reg n, size_t Vd, Imm<8> imm8) {
     if (!p && !u && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p && !w) {
-        ASSERT_MSG(false, "Decode error");
+        ASSERT(false && "Decode error");
     }
 
     if (p == u && w) {

src/dynarmic/src/dynarmic/frontend/A32/translate/translate_arm.cpp

@@ -77,7 +77,7 @@ IR::Block TranslateArm(LocationDescriptor descriptor, TranslateCallbacks* tcb, c
         }
     }
 
-    ASSERT_MSG(block.HasTerminal(), "Terminal has not been set");
+    ASSERT(block.HasTerminal() && "Terminal has not been set");
 
     block.SetEndLocation(visitor.ir.current_location);
 

src/dynarmic/src/dynarmic/frontend/A32/translate/translate_thumb.cpp

@@ -176,7 +176,7 @@ IR::Block TranslateThumb(LocationDescriptor descriptor, TranslateCallbacks* tcb,
         }
     }
 
-    ASSERT_MSG(block.HasTerminal(), "Terminal has not been set");
+    ASSERT(block.HasTerminal() && "Terminal has not been set");
 
     block.SetEndLocation(visitor.ir.current_location);
 

src/dynarmic/src/dynarmic/frontend/A64/translate/a64_translate.cpp

@@ -41,7 +41,7 @@ IR::Block Translate(LocationDescriptor descriptor, MemoryReadCodeFuncType memory
         visitor.ir.SetTerm(IR::Term::LinkBlock{*visitor.ir.current_location});
     }
 
-    ASSERT_MSG(block.HasTerminal(), "Terminal has not been set");
+    ASSERT(block.HasTerminal() && "Terminal has not been set");
 
     block.SetEndLocation(*visitor.ir.current_location);
 

src/dynarmic/src/dynarmic/frontend/imm.h

@@ -30,7 +30,7 @@ public:
 
     explicit Imm(u32 value)
             : value(value) {
-        ASSERT_MSG((mcl::bit::get_bits<0, bit_size - 1>(value) == value), "More bits in value than expected");
+        ASSERT((mcl::bit::get_bits<0, bit_size - 1>(value) == value) && "More bits in value than expected");
     }
 
     template<typename T = u32>

src/dynarmic/src/dynarmic/ir/basic_block.h

@@ -144,12 +144,12 @@ public:
     }
     /// Sets the terminal instruction for this basic block.
     inline void SetTerminal(Terminal term) noexcept {
-        ASSERT_MSG(!HasTerminal(), "Terminal has already been set.");
+        ASSERT(!HasTerminal() && "Terminal has already been set.");
         terminal = std::move(term);
     }
     /// Replaces the terminal instruction for this basic block.
     inline void ReplaceTerminal(Terminal term) noexcept {
-        ASSERT_MSG(HasTerminal(), "Terminal has not been set.");
+        ASSERT(HasTerminal() && "Terminal has not been set.");
         terminal = std::move(term);
     }
     /// Determines whether or not this basic block has a terminal instruction.

src/dynarmic/src/dynarmic/ir/ir_emitter.h

@@ -992,7 +992,7 @@ public:
     }
 
     UAny VectorGetElement(size_t esize, const U128& a, size_t index) {
-        ASSERT_MSG(esize * index < 128, "Invalid index");
+        ASSERT(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U8>(Opcode::VectorGetElement8, a, Imm8(static_cast<u8>(index)));
@@ -1008,7 +1008,7 @@ public:
     }
 
     U128 VectorSetElement(size_t esize, const U128& a, size_t index, const IR::UAny& elem) {
-        ASSERT_MSG(esize * index < 128, "Invalid index");
+        ASSERT(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorSetElement8, a, Imm8(static_cast<u8>(index)), elem);
@@ -1114,7 +1114,7 @@ public:
     }
 
     U128 VectorBroadcastElementLower(size_t esize, const U128& a, size_t index) {
-        ASSERT_MSG(esize * index < 128, "Invalid index");
+        ASSERT(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorBroadcastElementLower8, a, u8(index));
@@ -1127,7 +1127,7 @@ public:
     }
 
     U128 VectorBroadcastElement(size_t esize, const U128& a, size_t index) {
-        ASSERT_MSG(esize * index < 128, "Invalid index");
+        ASSERT(esize * index < 128 && "Invalid index");
         switch (esize) {
         case 8:
             return Inst<U128>(Opcode::VectorBroadcastElement8, a, u8(index));

src/dynarmic/src/dynarmic/ir/microinstruction.cpp

@@ -42,8 +42,8 @@ Type Inst::GetType() const {
 }
 
 void Inst::SetArg(size_t index, Value value) noexcept {
-    DEBUG_ASSERT_MSG(index < GetNumArgsOf(op), "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
-    DEBUG_ASSERT_MSG(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)), "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index));
+    DEBUG_ASSERT(index < GetNumArgsOf(op) && "Inst::SetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
+    DEBUG_ASSERT(AreTypesCompatible(value.GetType(), GetArgTypeOf(op, index)) && "Inst::SetArg: type {} of argument {} not compatible with operation {} ({})", value.GetType(), index, op, GetArgTypeOf(op, index));
     if (!args[index].IsImmediate()) {
         UndoUse(args[index]);
     }
@@ -79,7 +79,7 @@ void Inst::Use(const Value& value) {
 
     if (IsAPseudoOperation(op)) {
         if (op == Opcode::GetNZCVFromOp) {
-            ASSERT_MSG(MayGetNZCVFromOp(value.GetInst()->GetOpcode()), "This value doesn't support the GetNZCVFromOp pseduo-op");
+            ASSERT(MayGetNZCVFromOp(value.GetInst()->GetOpcode()) && "This value doesn't support the GetNZCVFromOp pseduo-op");
         }
 
         Inst* insert_point = value.GetInst();

src/dynarmic/src/dynarmic/ir/microinstruction.h

@@ -53,8 +53,8 @@ public:
     }
 
     inline Value GetArg(size_t index) const noexcept {
-        DEBUG_ASSERT_MSG(index < GetNumArgsOf(op), "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
-        DEBUG_ASSERT_MSG(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque, "Inst::GetArg: index {} is empty", index, args[index].GetType());
+        DEBUG_ASSERT(index < GetNumArgsOf(op) && "Inst::GetArg: index {} >= number of arguments of {} ({})", index, op, GetNumArgsOf(op));
+        DEBUG_ASSERT(!args[index].IsEmpty() || GetArgTypeOf(op, index) == IR::Type::Opaque && "Inst::GetArg: index {} is empty", index, args[index].GetType());
         return args[index];
     }
     void SetArg(size_t index, Value value) noexcept;

src/dynarmic/src/dynarmic/ir/opt_passes.cpp

@@ -1466,7 +1466,7 @@ static void VerificationPass(const IR::Block& block) {
         for (size_t i = 0; i < inst.NumArgs(); i++) {
             const IR::Type t1 = inst.GetArg(i).GetType();
             const IR::Type t2 = IR::GetArgTypeOf(inst.GetOpcode(), i);
-            ASSERT_MSG(IR::AreTypesCompatible(t1, t2), "Block failed:\n{}", IR::DumpBlock(block));
+            ASSERT(IR::AreTypesCompatible(t1, t2) && "Block failed:\n{}", IR::DumpBlock(block));
         }
     }
     ankerl::unordered_dense::map<IR::Inst*, size_t> actual_uses;

src/dynarmic/tests/A32/fuzz_arm.cpp

@@ -70,7 +70,7 @@ bool AnyLocationDescriptorForTerminalHas(IR::Terminal terminal, Fn fn) {
         } else if constexpr (std::is_same_v<T, IR::Term::CheckHalt>) {
             return AnyLocationDescriptorForTerminalHas(t.else_, fn);
         } else {
-            ASSERT_MSG(false, "Invalid terminal type");
+            ASSERT(false && "Invalid terminal type");
             return false;
         }
     }, terminal);

src/dynarmic/tests/A32/testenv.h

@@ -97,11 +97,11 @@ public:
         MemoryWrite32(vaddr + 4, static_cast<u32>(value >> 32));
     }
 
-    void InterpreterFallback(u32 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:08x}, {}) code = {:08x}", pc, num_instructions, *MemoryReadCode(pc)); }
+    void InterpreterFallback(u32 pc, size_t num_instructions) override { ASSERT(false, "InterpreterFallback({:08x} && {}) code = {:08x}", pc, num_instructions, *MemoryReadCode(pc)); }
 
-    void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
+    void CallSVC(std::uint32_t swi) override { ASSERT(false && "CallSVC({})", swi); }
 
-    void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc)); }
+    void ExceptionRaised(u32 pc, Dynarmic::A32::Exception /*exception*/) override { ASSERT(false && "ExceptionRaised({:08x}) code = {:08x}", pc, *MemoryReadCode(pc)); }
 
     void AddTicks(std::uint64_t ticks) override {
         if (ticks > ticks_left) {
@@ -184,11 +184,11 @@ public:
         return true;
     }
 
-    void InterpreterFallback(std::uint32_t pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
+    void InterpreterFallback(std::uint32_t pc, size_t num_instructions) override { ASSERT(false, "InterpreterFallback({:016x} && {})", pc, num_instructions); }
 
-    void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
+    void CallSVC(std::uint32_t swi) override { ASSERT(false && "CallSVC({})", swi); }
 
-    void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override { ASSERT_MSG(false, "ExceptionRaised({:016x})", pc); }
+    void ExceptionRaised(std::uint32_t pc, Dynarmic::A32::Exception) override { ASSERT(false && "ExceptionRaised({:016x})", pc); }
 
     void AddTicks(std::uint64_t ticks) override {
         if (ticks > ticks_left) {

src/dynarmic/tests/A64/testenv.h

@@ -105,11 +105,11 @@ public:
         return true;
     }
 
-    void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(false, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
+    void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT(false, "InterpreterFallback({:016x} && {})", pc, num_instructions); }
 
-    void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
+    void CallSVC(std::uint32_t swi) override { ASSERT(false && "CallSVC({})", swi); }
 
-    void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override { ASSERT_MSG(false, "ExceptionRaised({:016x})", pc); }
+    void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override { ASSERT(false && "ExceptionRaised({:016x})", pc); }
 
     void AddTicks(std::uint64_t ticks) override {
         if (ticks > ticks_left) {
@@ -202,11 +202,11 @@ public:
         return true;
     }
 
-    void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT_MSG(ignore_invalid_insn, "InterpreterFallback({:016x}, {})", pc, num_instructions); }
+    void InterpreterFallback(u64 pc, size_t num_instructions) override { ASSERT(ignore_invalid_insn, "InterpreterFallback({:016x} && {})", pc, num_instructions); }
 
-    void CallSVC(std::uint32_t swi) override { ASSERT_MSG(false, "CallSVC({})", swi); }
+    void CallSVC(std::uint32_t swi) override { ASSERT(false && "CallSVC({})", swi); }
 
-    void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override { ASSERT_MSG(false, "ExceptionRaised({:016x})", pc); }
+    void ExceptionRaised(u64 pc, Dynarmic::A64::Exception) override { ASSERT(false && "ExceptionRaised({:016x})", pc); }
 
     void AddTicks(std::uint64_t ticks) override {
         if (ticks > ticks_left) {

src/dynarmic/tests/unicorn_emu/a32_unicorn.cpp

@@ -18,7 +18,7 @@
 #define CHECKED(expr)                                                                                    \
     do {                                                                                                 \
         if (auto cerr_ = (expr)) {                                                                       \
-            ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", static_cast<size_t>(cerr_), \
+            ASSERT(false && "Call " #expr " failed with error: {} ({})\n", static_cast<size_t>(cerr_), \
                        uc_strerror(cerr_));                                                              \
         }                                                                                                \
     } while (0)

src/dynarmic/tests/unicorn_emu/a64_unicorn.cpp

@@ -13,7 +13,7 @@
 #define CHECKED(expr)                                                                                    \
     do {                                                                                                 \
         if (auto cerr_ = (expr)) {                                                                       \
-            ASSERT_MSG(false, "Call " #expr " failed with error: {} ({})\n", static_cast<size_t>(cerr_), \
+            ASSERT(false && "Call " #expr " failed with error: {} ({})\n", static_cast<size_t>(cerr_), \
                        uc_strerror(cerr_));                                                              \
         }                                                                                                \
     } while (0)