[dynarmic] simplify assert macro usage (Only ASSERT/DEBUG_ASSERT are needed)

Signed-off-by: lizzie <lizzie@eden-emu.dev>

src/dynarmic/src/dynarmic/backend/arm64/abi.h

@@ -63,7 +63,7 @@ constexpr RegisterList ToRegList(oaknut::Reg reg) {
     }
 
     if (reg.index() == 31) {
-        ASSERT_FALSE("ZR not allowed in reg list");
+        ASSERT(false && "ZR not allowed in reg list");
     }
 
     if (reg.index() == -1) {

src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp

@@ -258,7 +258,7 @@ void AddressSpace::Link(EmittedBlockInfo& block_info) {
             c.BL(prelude_info.get_ticks_remaining);
             break;
         default:
-            ASSERT_FALSE("Invalid relocation target");
+            ASSERT(false && "Invalid relocation target");
         }
     }
 
@@ -292,7 +292,7 @@ void AddressSpace::LinkBlockLinks(const CodePtr entry_point, const CodePtr targe
             }
             break;
         default:
-            ASSERT_FALSE("Invalid BlockRelocationType");
+            ASSERT(false && "Invalid BlockRelocationType");
         }
     }
 }
@@ -344,7 +344,7 @@ FakeCall AddressSpace::FastmemCallback(u64 host_pc) {
 fail:
     fmt::print("dynarmic: Segfault happened within JITted code at host_pc = {:016x}\n", host_pc);
     fmt::print("Segfault wasn't at a fastmem patch location!\n");
-    ASSERT_FALSE("segfault");
+    ASSERT(false && "segfault");
 }
 
 }  // namespace Dynarmic::Backend::Arm64

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp

@@ -112,7 +112,7 @@ void EmitIR<IR::Opcode::GetNZCVFromOp>(oaknut::CodeGenerator& code, EmitContext&
         break;
     }
     default:
-        ASSERT_FALSE("Invalid type for GetNZCVFromOp");
+        ASSERT(false && "Invalid type for GetNZCVFromOp");
         break;
     }
 }
@@ -143,7 +143,7 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
         break;
     }
     default:
-        ASSERT_FALSE("Invalid type for GetNZFromOp");
+        ASSERT(false && "Invalid type for GetNZFromOp");
         break;
     }
 }
@@ -241,7 +241,7 @@ EmittedBlockInfo EmitArm64(oaknut::CodeGenerator& code, IR::Block block, const E
 #undef A32OPC
 #undef A64OPC
         default:
-            ASSERT_FALSE("Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
+            ASSERT(false && "Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
             break;
         }
 

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32.cpp

@@ -34,7 +34,7 @@ oaknut::Label EmitA32Cond(oaknut::CodeGenerator& code, EmitContext&, IR::Cond co
 void EmitA32Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::Terminal terminal, IR::LocationDescriptor initial_location, bool is_single_step);
 
 void EmitA32Terminal(oaknut::CodeGenerator&, EmitContext&, IR::Term::Interpret, IR::LocationDescriptor, bool) {
-    ASSERT_FALSE("Interpret should never be emitted.");
+    ASSERT(false && "Interpret should never be emitted.");
 }
 
 void EmitA32Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::ReturnToDispatch, IR::LocationDescriptor, bool) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a32_coprocessor.cpp

@@ -20,7 +20,7 @@ namespace Dynarmic::Backend::Arm64 {
 using namespace oaknut::util;
 
 static void EmitCoprocessorException() {
-    ASSERT_FALSE("Should raise coproc exception here");
+    ASSERT(false && "Should raise coproc exception here");
 }
 
 static void CallCoprocCallback(oaknut::CodeGenerator& code, EmitContext& ctx, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_a64.cpp

@@ -36,7 +36,7 @@ oaknut::Label EmitA64Cond(oaknut::CodeGenerator& code, EmitContext&, IR::Cond co
 void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::Terminal terminal, IR::LocationDescriptor initial_location, bool is_single_step);
 
 void EmitA64Terminal(oaknut::CodeGenerator&, EmitContext&, IR::Term::Interpret, IR::LocationDescriptor, bool) {
-    ASSERT_FALSE("Interpret should never be emitted.");
+    ASSERT(false && "Interpret should never be emitted.");
 }
 
 void EmitA64Terminal(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Term::ReturnToDispatch, IR::LocationDescriptor, bool) {

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp

@@ -117,7 +117,7 @@ void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp

@@ -123,10 +123,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
                 code.FCVTAS(Rto, Vfrom);
                 break;
             case FP::RoundingMode::ToOdd:
-                ASSERT_FALSE("Unimplemented");
+                ASSERT(false && "Unimplemented");
                 break;
             default:
-                ASSERT_FALSE("Invalid RoundingMode");
+                ASSERT(false && "Invalid RoundingMode");
                 break;
             }
         } else {
@@ -147,10 +147,10 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
                 code.FCVTAU(Rto, Vfrom);
                 break;
             case FP::RoundingMode::ToOdd:
-                ASSERT_FALSE("Unimplemented");
+                ASSERT(false && "Unimplemented");
                 break;
             default:
-                ASSERT_FALSE("Invalid RoundingMode");
+                ASSERT(false && "Invalid RoundingMode");
                 break;
             }
         }
@@ -188,7 +188,7 @@ void EmitIR<IR::Opcode::FPAbs16>(oaknut::CodeGenerator& code, EmitContext& ctx,
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -315,7 +315,7 @@ void EmitIR<IR::Opcode::FPMulAdd16>(oaknut::CodeGenerator& code, EmitContext& ct
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -333,7 +333,7 @@ void EmitIR<IR::Opcode::FPMulSub16>(oaknut::CodeGenerator& code, EmitContext& ct
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -361,7 +361,7 @@ void EmitIR<IR::Opcode::FPNeg16>(oaknut::CodeGenerator& code, EmitContext& ctx,
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -379,7 +379,7 @@ void EmitIR<IR::Opcode::FPRecipEstimate16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -397,7 +397,7 @@ void EmitIR<IR::Opcode::FPRecipExponent16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -415,7 +415,7 @@ void EmitIR<IR::Opcode::FPRecipStepFused16>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -433,7 +433,7 @@ void EmitIR<IR::Opcode::FPRoundInt16>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -468,7 +468,7 @@ void EmitIR<IR::Opcode::FPRoundInt32>(oaknut::CodeGenerator& code, EmitContext&
             code.FRINTA(Sresult, Soperand);
             break;
         default:
-            ASSERT_FALSE("Invalid RoundingMode");
+            ASSERT(false && "Invalid RoundingMode");
         }
     }
 }
@@ -505,7 +505,7 @@ void EmitIR<IR::Opcode::FPRoundInt64>(oaknut::CodeGenerator& code, EmitContext&
             code.FRINTA(Dresult, Doperand);
             break;
         default:
-            ASSERT_FALSE("Invalid RoundingMode");
+            ASSERT(false && "Invalid RoundingMode");
         }
     }
 }
@@ -515,7 +515,7 @@ void EmitIR<IR::Opcode::FPRSqrtEstimate16>(oaknut::CodeGenerator& code, EmitCont
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -533,7 +533,7 @@ void EmitIR<IR::Opcode::FPRSqrtStepFused16>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -647,7 +647,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -655,7 +655,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS32>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -663,7 +663,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS64>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -671,7 +671,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -679,7 +679,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU32>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -687,7 +687,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU64>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp

@@ -315,7 +315,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.DMB(oaknut::BarrierOp::ISH);
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
     } else {
         fastmem_location = code.xptr<CodePtr>();
@@ -337,7 +337,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.LDR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
     }
 
@@ -376,7 +376,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.DMB(oaknut::BarrierOp::ISH);
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
     } else {
         fastmem_location = code.xptr<CodePtr>();
@@ -398,7 +398,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
             code.STR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
     }
 

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp

@@ -131,7 +131,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd8>(oaknut::CodeGenerator& code, EmitCo
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -139,7 +139,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd16>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -147,7 +147,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd32>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -155,7 +155,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd64>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -163,7 +163,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(oaknut::Cod
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -171,7 +171,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(oaknut::Cod
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -179,7 +179,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub8>(oaknut::CodeGenerator& code, EmitCo
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -187,7 +187,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub16>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -195,7 +195,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub32>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -203,7 +203,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub64>(oaknut::CodeGenerator& code, EmitC
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -211,7 +211,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(oaknut::CodeGenerator& code, Emit
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -219,7 +219,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -227,7 +227,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -235,7 +235,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -243,7 +243,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(oaknut::CodeGenerator& code, Emit
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -251,7 +251,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -259,7 +259,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -267,7 +267,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 }  // namespace Dynarmic::Backend::Arm64

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp

@@ -638,7 +638,7 @@ void EmitIR<IR::Opcode::VectorEqual128>(oaknut::CodeGenerator& code, EmitContext
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -867,7 +867,7 @@ void EmitIR<IR::Opcode::VectorMaxS64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -890,7 +890,7 @@ void EmitIR<IR::Opcode::VectorMaxU64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -913,7 +913,7 @@ void EmitIR<IR::Opcode::VectorMinS64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -936,7 +936,7 @@ void EmitIR<IR::Opcode::VectorMinU64>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -1383,7 +1383,7 @@ void EmitIR<IR::Opcode::VectorSignExtend64>(oaknut::CodeGenerator& code, EmitCon
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -1406,7 +1406,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply16>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -1414,7 +1414,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply32>(oaknut::CodeGenerator& code, Emi
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -1666,7 +1666,7 @@ void EmitIR<IR::Opcode::VectorTableLookup64>(oaknut::CodeGenerator& code, EmitCo
         }
         break;
     default:
-        ASSERT_FALSE("Unsupported table_size");
+        ASSERT(false && "Unsupported table_size");
     }
 }
 
@@ -1730,7 +1730,7 @@ void EmitIR<IR::Opcode::VectorTableLookup128>(oaknut::CodeGenerator& code, EmitC
         }
         break;
     default:
-        ASSERT_FALSE("Unsupported table_size");
+        ASSERT(false && "Unsupported table_size");
     }
 }
 
@@ -1778,7 +1778,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -1786,7 +1786,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply32>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>

src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp

@@ -227,10 +227,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                     code.FCVTAS(Vto, Vfrom);
                     break;
                 case FP::RoundingMode::ToOdd:
-                    ASSERT_FALSE("Unimplemented");
+                    ASSERT(false && "Unimplemented");
                     break;
                 default:
-                    ASSERT_FALSE("Invalid RoundingMode");
+                    ASSERT(false && "Invalid RoundingMode");
                     break;
                 }
             } else {
@@ -251,10 +251,10 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
                     code.FCVTAU(Vto, Vfrom);
                     break;
                 case FP::RoundingMode::ToOdd:
-                    ASSERT_FALSE("Unimplemented");
+                    ASSERT(false && "Unimplemented");
                     break;
                 default:
-                    ASSERT_FALSE("Invalid RoundingMode");
+                    ASSERT(false && "Invalid RoundingMode");
                     break;
                 }
             }
@@ -340,7 +340,7 @@ void EmitIR<IR::Opcode::FPVectorEqual16>(oaknut::CodeGenerator& code, EmitContex
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -465,7 +465,7 @@ void EmitIR<IR::Opcode::FPVectorMulAdd16>(oaknut::CodeGenerator& code, EmitConte
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -493,7 +493,7 @@ void EmitIR<IR::Opcode::FPVectorNeg16>(oaknut::CodeGenerator& code, EmitContext&
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -538,7 +538,7 @@ void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -556,7 +556,7 @@ void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -648,7 +648,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt32>(oaknut::CodeGenerator& code, EmitCon
                 code.FRINTA(Qresult->S4(), Qoperand->S4());
                 break;
             default:
-                ASSERT_FALSE("Invalid RoundingMode");
+                ASSERT(false && "Invalid RoundingMode");
             }
         }
     });
@@ -688,7 +688,7 @@ void EmitIR<IR::Opcode::FPVectorRoundInt64>(oaknut::CodeGenerator& code, EmitCon
                 code.FRINTA(Qresult->D2(), Qoperand->D2());
                 break;
             default:
-                ASSERT_FALSE("Invalid RoundingMode");
+                ASSERT(false && "Invalid RoundingMode");
             }
         }
     });
@@ -699,7 +699,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -717,7 +717,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(oaknut::CodeGenerator& code, E
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -772,7 +772,7 @@ void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(oaknut::CodeGenerator& code, Em
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>
@@ -790,7 +790,7 @@ void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(oaknut::CodeGenerator& code,
     (void)code;
     (void)ctx;
     (void)inst;
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 }
 
 template<>

src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp

@@ -328,7 +328,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
         switch (current_location->kind) {
         case HostLoc::Kind::Gpr:
-            ASSERT_FALSE("Logic error");
+            ASSERT(false && "Logic error");
             break;
         case HostLoc::Kind::Fpr:
             code.FMOV(oaknut::XReg{new_location_index}, oaknut::DReg{current_location->index});
@@ -354,13 +354,13 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
             code.FMOV(oaknut::DReg{new_location_index}, oaknut::XReg{current_location->index});
             break;
         case HostLoc::Kind::Fpr:
-            ASSERT_FALSE("Logic error");
+            ASSERT(false && "Logic error");
             break;
         case HostLoc::Kind::Spill:
             code.LDR(oaknut::QReg{new_location_index}, SP, spill_offset + current_location->index * spill_slot_size);
             break;
         case HostLoc::Kind::Flags:
-            ASSERT_FALSE("Moving from flags into fprs is not currently supported");
+            ASSERT(false && "Moving from flags into fprs is not currently supported");
             break;
         }
 
@@ -368,7 +368,7 @@ int RegAlloc::RealizeReadImpl(const IR::Value& value) {
         fprs[new_location_index].realized = true;
         return new_location_index;
     } else if constexpr (required_kind == HostLoc::Kind::Flags) {
-        ASSERT_FALSE("A simple read from flags is likely a logic error.");
+        ASSERT(false && "A simple read from flags is likely a logic error.");
     } else {
         static_assert(Common::always_false_v<mcl::mp::lift_value<required_kind>>);
     }
@@ -414,7 +414,7 @@ int RegAlloc::RealizeReadWriteImpl(const IR::Value& read_value, const IR::Inst*
         LoadCopyInto(read_value, oaknut::QReg{write_loc});
         return write_loc;
     } else if constexpr (kind == HostLoc::Kind::Flags) {
-        ASSERT_FALSE("Incorrect function for ReadWrite of flags");
+        ASSERT(false && "Incorrect function for ReadWrite of flags");
     } else {
         static_assert(Common::always_false_v<mcl::mp::lift_value<kind>>);
     }
@@ -486,7 +486,7 @@ void RegAlloc::ReadWriteFlags(Argument& read, IR::Inst* write) {
         code.LDR(Wscratch0, SP, spill_offset + current_location->index * spill_slot_size);
         code.MSR(oaknut::SystemReg::NZCV, Xscratch0);
     } else {
-        ASSERT_FALSE("Invalid current location for flags");
+        ASSERT(false && "Invalid current location for flags");
     }
 
     if (write) {
@@ -558,7 +558,7 @@ void RegAlloc::LoadCopyInto(const IR::Value& value, oaknut::QReg reg) {
         code.LDR(reg, SP, spill_offset + current_location->index * spill_slot_size);
         break;
     case HostLoc::Kind::Flags:
-        ASSERT_FALSE("Moving from flags into fprs is not currently supported");
+        ASSERT(false && "Moving from flags into fprs is not currently supported");
         break;
     }
 }
@@ -592,7 +592,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
     case HostLoc::Kind::Spill:
         return spills[static_cast<size_t>(host_loc.index)];
     }
-    ASSERT_FALSE("RegAlloc::ValueInfo: Invalid HostLoc::Kind");
+    ASSERT(false && "RegAlloc::ValueInfo: Invalid HostLoc::Kind");
 }
 
 HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@@ -610,7 +610,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
     if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != spills.end()) {
         return *iter;
     }
-    ASSERT_FALSE("RegAlloc::ValueInfo: Value not found");
+    ASSERT(false && "RegAlloc::ValueInfo: Value not found");
 }
 
 }  // namespace Dynarmic::Backend::Arm64

src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h

@@ -182,7 +182,7 @@ public:
         } else if constexpr (size == 32) {
             return ReadW(arg);
         } else {
-            ASSERT_FALSE("Invalid size to ReadReg {}", size);
+            ASSERT(false && "Invalid size to ReadReg {}", size);
         }
     }
 
@@ -199,7 +199,7 @@ public:
         } else if constexpr (size == 8) {
             return ReadB(arg);
         } else {
-            ASSERT_FALSE("Invalid size to ReadVec {}", size);
+            ASSERT(false && "Invalid size to ReadVec {}", size);
         }
     }
 
@@ -221,7 +221,7 @@ public:
         } else if constexpr (size == 32) {
             return WriteW(inst);
         } else {
-            ASSERT_FALSE("Invalid size to WriteReg {}", size);
+            ASSERT(false && "Invalid size to WriteReg {}", size);
         }
     }
 
@@ -238,7 +238,7 @@ public:
         } else if constexpr (size == 8) {
             return WriteB(inst);
         } else {
-            ASSERT_FALSE("Invalid size to WriteVec {}", size);
+            ASSERT(false && "Invalid size to WriteVec {}", size);
         }
     }
 
@@ -258,7 +258,7 @@ public:
         } else if constexpr (size == 32) {
             return ReadWriteW(arg, inst);
         } else {
-            ASSERT_FALSE("Invalid size to ReadWriteReg {}", size);
+            ASSERT(false && "Invalid size to ReadWriteReg {}", size);
         }
     }
 
@@ -275,7 +275,7 @@ public:
         } else if constexpr (size == 8) {
             return ReadWriteB(arg, inst);
         } else {
-            ASSERT_FALSE("Invalid size to ReadWriteVec {}", size);
+            ASSERT(false && "Invalid size to ReadWriteVec {}", size);
         }
     }
 
@@ -372,7 +372,7 @@ void RAReg<T>::Realize() {
         reg = T{reg_alloc.RealizeReadWriteImpl<kind>(read_value, write_value)};
         break;
     default:
-        ASSERT_FALSE("Invalid RWType");
+        ASSERT(false && "Invalid RWType");
     }
 }
 

src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp

@@ -139,7 +139,7 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) {
     }
     fmt::print(stderr, "Unhandled {} at pc {:#018x}\n", sig == SIGSEGV ? "SIGSEGV" : "SIGBUS", CTX_PC);
 #elif defined(ARCHITECTURE_riscv64)
-    ASSERT_FALSE("Unimplemented");
+    ASSERT(false && "Unimplemented");
 #else
 #    error "Invalid architecture"
 #endif

src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp

@@ -128,7 +128,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
             break;
         }
         default:
-            ASSERT_FALSE("Invalid relocation target");
+            ASSERT(false && "Invalid relocation target");
         }
     }
 }

src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp

@@ -121,7 +121,7 @@ struct Jit::Impl final {
 
 private:
     void RequestCacheInvalidation() {
-        // ASSERT_FALSE("Unimplemented");
+        // ASSERT(false && "Unimplemented");
 
         invalidate_entire_cache = false;
         invalid_cache_ranges.clear();

src/dynarmic/src/dynarmic/backend/riscv64/code_block.h

@@ -17,7 +17,7 @@ public:
     explicit CodeBlock(std::size_t size) noexcept : memsize(size) {
         mem = (u8*)mmap(nullptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_ANON | MAP_PRIVATE, -1, 0);
         if (mem == nullptr)
-            ASSERT_FALSE("out of memory");
+            ASSERT(false && "out of memory");
     }
 
     ~CodeBlock() noexcept {

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64.cpp

@@ -143,7 +143,7 @@ EmittedBlockInfo EmitRV64(biscuit::Assembler& as, IR::Block block, const EmitCon
 #undef A32OPC
 #undef A64OPC
         default:
-            ASSERT_FALSE("Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
+            ASSERT(false && "Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
             break;
         }
     }

src/dynarmic/src/dynarmic/backend/riscv64/emit_riscv64_a32.cpp

@@ -113,7 +113,7 @@ void EmitA32Cond(biscuit::Assembler& as, EmitContext&, IR::Cond cond, biscuit::L
 void EmitA32Terminal(biscuit::Assembler& as, EmitContext& ctx, IR::Term::Terminal terminal, IR::LocationDescriptor initial_location, bool is_single_step);
 
 void EmitA32Terminal(biscuit::Assembler&, EmitContext&, IR::Term::Interpret, IR::LocationDescriptor, bool) {
-    ASSERT_FALSE("Interpret should never be emitted.");
+    ASSERT(false && "Interpret should never be emitted.");
 }
 
 void EmitA32Terminal(biscuit::Assembler& as, EmitContext& ctx, IR::Term::ReturnToDispatch, IR::LocationDescriptor, bool) {

src/dynarmic/src/dynarmic/backend/riscv64/reg_alloc.cpp

@@ -193,7 +193,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
 
         switch (current_location->kind) {
         case HostLoc::Kind::Gpr:
-            ASSERT_FALSE("Logic error");
+            ASSERT(false && "Logic error");
             break;
         case HostLoc::Kind::Fpr:
             as.FMV_X_D(biscuit::GPR(new_location_index), biscuit::FPR{current_location->index});
@@ -216,7 +216,7 @@ u32 RegAlloc::RealizeReadImpl(const IR::Value& value) {
             as.FMV_D_X(biscuit::FPR{new_location_index}, biscuit::GPR(current_location->index));
             break;
         case HostLoc::Kind::Fpr:
-            ASSERT_FALSE("Logic error");
+            ASSERT(false && "Logic error");
             break;
         case HostLoc::Kind::Spill:
             as.FLD(biscuit::FPR{new_location_index}, spill_offset + current_location->index * spill_slot_size, biscuit::sp);
@@ -329,7 +329,7 @@ HostLocInfo& RegAlloc::ValueInfo(HostLoc host_loc) {
     case HostLoc::Kind::Spill:
         return spills[static_cast<size_t>(host_loc.index)];
     }
-    ASSERT_FALSE("RegAlloc::ValueInfo: Invalid HostLoc::Kind");
+    ASSERT(false && "RegAlloc::ValueInfo: Invalid HostLoc::Kind");
 }
 
 HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
@@ -346,7 +346,7 @@ HostLocInfo& RegAlloc::ValueInfo(const IR::Inst* value) {
     if (const auto iter = std::find_if(spills.begin(), spills.end(), contains_value); iter != gprs.end()) {
         return *iter;
     }
-    ASSERT_FALSE("RegAlloc::ValueInfo: Value not found");
+    ASSERT(false && "RegAlloc::ValueInfo: Value not found");
 }
 
 }  // namespace Dynarmic::Backend::RV64

src/dynarmic/src/dynarmic/backend/x64/a32_emit_x64.cpp

@@ -59,7 +59,7 @@ static Xbyak::Address MJitStateExtReg(A32::ExtReg reg) {
         const size_t index = static_cast<size_t>(reg) - static_cast<size_t>(A32::ExtReg::Q0);
         return xword[BlockOfCode::ABI_JIT_PTR + offsetof(A32JitState, ExtReg) + 2 * sizeof(u64) * index];
     }
-    ASSERT_FALSE("Should never happen.");
+    ASSERT(false && "Should never happen.");
 }
 
 A32EmitContext::A32EmitContext(const A32::UserConfig& conf, RegAlloc& reg_alloc, IR::Block& block)
@@ -144,7 +144,7 @@ A32EmitX64::BlockDescriptor A32EmitX64::Emit(IR::Block& block) {
 #undef OPCODE
 #undef A32OPC
 #undef A64OPC
-            default: [[unlikely]] ASSERT_FALSE("Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
+            default: [[unlikely]] ASSERT(false && "Invalid opcode: {:x}", std::size_t(inst->GetOpcode()));
             }
             reg_alloc.EndOfAllocScope();
             func(reg_alloc);
@@ -846,7 +846,7 @@ void A32EmitX64::EmitA32SetFpscrNZCV(A32EmitContext& ctx, IR::Inst* inst) {
 }
 
 static void EmitCoprocessorException() {
-    ASSERT_FALSE("Should raise coproc exception here");
+    ASSERT(false && "Should raise coproc exception here");
 }
 
 static void CallCoprocCallback(BlockOfCode& code, RegAlloc& reg_alloc, A32::Coprocessor::Callback callback, IR::Inst* inst = nullptr, std::optional<Argument::copyable_reference> arg0 = {}, std::optional<Argument::copyable_reference> arg1 = {}) {

src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h

@@ -243,7 +243,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
             }
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
         return fastmem_location;
     } else {
@@ -265,7 +265,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
             code.movups(Xbyak::Xmm(value_idx), xword[addr]);
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
         return fastmem_location;
     }
@@ -311,7 +311,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
             break;
         }
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
         return fastmem_location;
     } else {
@@ -333,7 +333,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
             code.movups(xword[addr], Xbyak::Xmm(value_idx));
             break;
         default:
-            ASSERT_FALSE("Invalid bitsize");
+            ASSERT(false && "Invalid bitsize");
         }
         return fastmem_location;
     }

src/dynarmic/src/dynarmic/backend/x64/emit_x64_vector.cpp

@@ -2425,27 +2425,27 @@ void EmitX64::EmitVectorMultiply64(EmitContext& ctx, IR::Inst* inst) {
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden8(EmitContext&, IR::Inst*) {
-    ASSERT_FALSE("Unexpected VectorMultiplySignedWiden8");
+    ASSERT(false && "Unexpected VectorMultiplySignedWiden8");
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden16(EmitContext&, IR::Inst*) {
-    ASSERT_FALSE("Unexpected VectorMultiplySignedWiden16");
+    ASSERT(false && "Unexpected VectorMultiplySignedWiden16");
 }
 
 void EmitX64::EmitVectorMultiplySignedWiden32(EmitContext&, IR::Inst*) {
-    ASSERT_FALSE("Unexpected VectorMultiplySignedWiden32");
+    ASSERT(false && "Unexpected VectorMultiplySignedWiden32");
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden8(EmitContext&, IR::Inst*) {
-    ASSERT_FALSE("Unexpected VectorMultiplyUnsignedWiden8");
+    ASSERT(false && "Unexpected VectorMultiplyUnsignedWiden8");
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden16(EmitContext&, IR::Inst*) {
-    ASSERT_FALSE("Unexpected VectorMultiplyUnsignedWiden16");
+    ASSERT(false && "Unexpected VectorMultiplyUnsignedWiden16");
 }
 
 void EmitX64::EmitVectorMultiplyUnsignedWiden32(EmitContext&, IR::Inst*) {
-    ASSERT_FALSE("Unexpected VectorMultiplyUnsignedWiden32");
+    ASSERT(false && "Unexpected VectorMultiplyUnsignedWiden32");
 }
 
 void EmitX64::EmitVectorNarrow16(EmitContext& ctx, IR::Inst* inst) {

src/dynarmic/src/dynarmic/backend/x64/reg_alloc.cpp

@@ -49,9 +49,9 @@ static inline size_t GetBitWidth(const IR::Type type) noexcept {
     case IR::Type::Void:
     case IR::Type::Table:
     case IR::Type::AccType:
-        ASSERT_FALSE("Type {} cannot be represented at runtime", type);
+        ASSERT(false && "Type {} cannot be represented at runtime", type);
     case IR::Type::Opaque:
-        ASSERT_FALSE("Not a concrete type");
+        ASSERT(false && "Not a concrete type");
     case IR::Type::U1:
         return 8;
     case IR::Type::U8:
@@ -582,7 +582,7 @@ HostLoc RegAlloc::FindFreeSpill(bool is_xmm) const noexcept {
     for (size_t i = size_t(HostLoc::FirstSpill); i < hostloc_info.size(); ++i)
         if (const auto loc = HostLoc(i); LocInfo(loc).IsEmpty())
             return loc;
-    ASSERT_FALSE("All spill locations are full");
+    ASSERT(false && "All spill locations are full");
 };
 
 void RegAlloc::EmitMove(const size_t bit_width, const HostLoc to, const HostLoc from) noexcept {
@@ -669,7 +669,7 @@ void RegAlloc::EmitMove(const size_t bit_width, const HostLoc to, const HostLoc
             code->mov(Xbyak::util::dword[spill_to_op_arg_helper(to, reserved_stack_space)], HostLocToReg64(from).cvt32());
         }
     } else {
-        ASSERT_FALSE("Invalid RegAlloc::EmitMove");
+        ASSERT(false && "Invalid RegAlloc::EmitMove");
     }
 }
 
@@ -677,9 +677,9 @@ void RegAlloc::EmitExchange(const HostLoc a, const HostLoc b) noexcept {
     if (HostLocIsGPR(a) && HostLocIsGPR(b)) {
         code->xchg(HostLocToReg64(a), HostLocToReg64(b));
     } else if (HostLocIsXMM(a) && HostLocIsXMM(b)) {
-        ASSERT_FALSE("Check your code: Exchanging XMM registers is unnecessary");
+        ASSERT(false && "Check your code: Exchanging XMM registers is unnecessary");
     } else {
-        ASSERT_FALSE("Invalid RegAlloc::EmitExchange");
+        ASSERT(false && "Invalid RegAlloc::EmitExchange");
     }
 }
 

src/dynarmic/src/dynarmic/common/fp/process_exception.cpp

@@ -19,37 +19,37 @@ void FPProcessException(FPExc exception, FPCR fpcr, FPSR& fpsr) {
     switch (exception) {
     case FPExc::InvalidOp:
         if (fpcr.IOE()) {
-            ASSERT_FALSE("Raising floating point exceptions unimplemented");
+            ASSERT(false && "Raising floating point exceptions unimplemented");
         }
         fpsr.IOC(true);
         break;
     case FPExc::DivideByZero:
         if (fpcr.DZE()) {
-            ASSERT_FALSE("Raising floating point exceptions unimplemented");
+            ASSERT(false && "Raising floating point exceptions unimplemented");
         }
         fpsr.DZC(true);
         break;
     case FPExc::Overflow:
         if (fpcr.OFE()) {
-            ASSERT_FALSE("Raising floating point exceptions unimplemented");
+            ASSERT(false && "Raising floating point exceptions unimplemented");
         }
         fpsr.OFC(true);
         break;
     case FPExc::Underflow:
         if (fpcr.UFE()) {
-            ASSERT_FALSE("Raising floating point exceptions unimplemented");
+            ASSERT(false && "Raising floating point exceptions unimplemented");
         }
         fpsr.UFC(true);
         break;
     case FPExc::Inexact:
         if (fpcr.IXE()) {
-            ASSERT_FALSE("Raising floating point exceptions unimplemented");
+            ASSERT(false && "Raising floating point exceptions unimplemented");
         }
         fpsr.IXC(true);
         break;
     case FPExc::InputDenorm:
         if (fpcr.IDE()) {
-            ASSERT_FALSE("Raising floating point exceptions unimplemented");
+            ASSERT(false && "Raising floating point exceptions unimplemented");
         }
         fpsr.IDC(true);
         break;

src/dynarmic/src/dynarmic/frontend/A32/a32_ir_emitter.cpp

@@ -64,7 +64,7 @@ IR::U32U64 IREmitter::GetExtendedRegister(ExtReg reg) {
         return Inst<IR::U32U64>(Opcode::A32GetExtendedRegister64, IR::Value(reg));
     }
 
-    ASSERT_FALSE("Invalid reg.");
+    ASSERT(false && "Invalid reg.");
 }
 
 IR::U128 IREmitter::GetVector(ExtReg reg) {
@@ -83,7 +83,7 @@ void IREmitter::SetExtendedRegister(const ExtReg reg, const IR::U32U64& value) {
     } else if (A32::IsDoubleExtReg(reg)) {
         Inst(Opcode::A32SetExtendedRegister64, IR::Value(reg), value);
     } else {
-        ASSERT_FALSE("Invalid reg.");
+        ASSERT(false && "Invalid reg.");
     }
 }
 
@@ -240,7 +240,7 @@ IR::UAny IREmitter::ReadMemory(size_t bitsize, const IR::U32& vaddr, IR::AccType
     case 64:
         return ReadMemory64(vaddr, acc_type);
     }
-    ASSERT_FALSE("Invalid bitsize");
+    ASSERT(false && "Invalid bitsize");
 }
 
 IR::U8 IREmitter::ReadMemory8(const IR::U32& vaddr, IR::AccType acc_type) {
@@ -298,7 +298,7 @@ void IREmitter::WriteMemory(size_t bitsize, const IR::U32& vaddr, const IR::UAny
     case 64:
         return WriteMemory64(vaddr, value, acc_type);
     }
-    ASSERT_FALSE("Invalid bitsize");
+    ASSERT(false && "Invalid bitsize");
 }
 
 void IREmitter::WriteMemory8(const IR::U32& vaddr, const IR::U8& value, IR::AccType acc_type) {

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/a32_translate_impl.cpp

@@ -71,7 +71,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
     case 64:
         return ir.Imm64(value);
     default:
-        ASSERT_FALSE("Imm - get: Invalid bitsize");
+        ASSERT(false && "Imm - get: Invalid bitsize");
     }
 }
 

src/dynarmic/src/dynarmic/frontend/A32/translate/impl/asimd_load_store_structures.cpp

@@ -69,7 +69,7 @@ std::optional<std::tuple<size_t, size_t, size_t>> DecodeType(Imm<4> type, size_t
         }
         return std::tuple<size_t, size_t, size_t>{4, 1, 2};
     }
-    ASSERT_FALSE("Decode error");
+    ASSERT(false && "Decode error");
 }
 }  // namespace
 

src/dynarmic/src/dynarmic/frontend/A64/translate/impl/impl.cpp

@@ -76,7 +76,7 @@ IR::UAny TranslatorVisitor::I(size_t bitsize, u64 value) {
     case 64:
         return ir.Imm64(value);
     default:
-        ASSERT_FALSE("Imm - get: Invalid bitsize");
+        ASSERT(false && "Imm - get: Invalid bitsize");
     }
 }
 
@@ -91,7 +91,7 @@ IR::UAny TranslatorVisitor::X(size_t bitsize, Reg reg) {
     case 64:
         return ir.GetX(reg);
     default:
-        ASSERT_FALSE("X - get: Invalid bitsize");
+        ASSERT(false && "X - get: Invalid bitsize");
     }
 }
 
@@ -104,7 +104,7 @@ void TranslatorVisitor::X(size_t bitsize, Reg reg, IR::U32U64 value) {
         ir.SetX(reg, value);
         return;
     default:
-        ASSERT_FALSE("X - set: Invalid bitsize");
+        ASSERT(false && "X - set: Invalid bitsize");
     }
 }
 
@@ -115,7 +115,7 @@ IR::U32U64 TranslatorVisitor::SP(size_t bitsize) {
     case 64:
         return ir.GetSP();
     default:
-        ASSERT_FALSE("SP - get : Invalid bitsize");
+        ASSERT(false && "SP - get : Invalid bitsize");
     }
 }
 
@@ -128,7 +128,7 @@ void TranslatorVisitor::SP(size_t bitsize, IR::U32U64 value) {
         ir.SetSP(value);
         break;
     default:
-        ASSERT_FALSE("SP - set : Invalid bitsize");
+        ASSERT(false && "SP - set : Invalid bitsize");
     }
 }
 
@@ -141,7 +141,7 @@ IR::U128 TranslatorVisitor::V(size_t bitsize, Vec vec) {
     case 128:
         return ir.GetQ(vec);
     default:
-        ASSERT_FALSE("V - get : Invalid bitsize");
+        ASSERT(false && "V - get : Invalid bitsize");
     }
 }
 
@@ -158,7 +158,7 @@ void TranslatorVisitor::V(size_t bitsize, Vec vec, IR::U128 value) {
         ir.SetQ(vec, value);
         return;
     default:
-        ASSERT_FALSE("V - Set : Invalid bitsize");
+        ASSERT(false && "V - Set : Invalid bitsize");
     }
 }
 
@@ -233,7 +233,7 @@ IR::UAnyU128 TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccTyp
     case 16:
         return ir.ReadMemory128(address, acc_type);
     default:
-        ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
+        ASSERT(false && "Invalid bytesize parameter {}", bytesize);
     }
 }
 
@@ -255,7 +255,7 @@ void TranslatorVisitor::Mem(IR::U64 address, size_t bytesize, IR::AccType acc_ty
         ir.WriteMemory128(address, value, acc_type);
         return;
     default:
-        ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
+        ASSERT(false && "Invalid bytesize parameter {}", bytesize);
     }
 }
 
@@ -272,7 +272,7 @@ IR::UAnyU128 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, I
     case 16:
         return ir.ExclusiveReadMemory128(address, acc_type);
     default:
-        ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
+        ASSERT(false && "Invalid bytesize parameter {}", bytesize);
     }
 }
 
@@ -289,7 +289,7 @@ IR::U32 TranslatorVisitor::ExclusiveMem(IR::U64 address, size_t bytesize, IR::Ac
     case 16:
         return ir.ExclusiveWriteMemory128(address, value, acc_type);
     default:
-        ASSERT_FALSE("Invalid bytesize parameter {}", bytesize);
+        ASSERT(false && "Invalid bytesize parameter {}", bytesize);
     }
 }
 
@@ -300,7 +300,7 @@ IR::U32U64 TranslatorVisitor::SignExtend(IR::UAny value, size_t to_size) {
     case 64:
         return ir.SignExtendToLong(value);
     default:
-        ASSERT_FALSE("Invalid size parameter {}", to_size);
+        ASSERT(false && "Invalid size parameter {}", to_size);
     }
 }
 
@@ -311,7 +311,7 @@ IR::U32U64 TranslatorVisitor::ZeroExtend(IR::UAny value, size_t to_size) {
     case 64:
         return ir.ZeroExtendToLong(value);
     default:
-        ASSERT_FALSE("Invalid size parameter {}", to_size);
+        ASSERT(false && "Invalid size parameter {}", to_size);
     }
 }
 

src/dynarmic/src/dynarmic/frontend/A64/translate/impl/simd_scalar_x_indexed_element.cpp

@@ -72,11 +72,11 @@ bool MultiplyByElementHalfPrecision(TranslatorVisitor& v, Imm<1> L, Imm<1> M, Im
         //       for regular multiplication and extended multiplication.
 
         if (extra_behavior == ExtraBehavior::None) {
-            ASSERT_FALSE("half-precision option unimplemented");
+            ASSERT(false && "half-precision option unimplemented");
         }
 
         if (extra_behavior == ExtraBehavior::MultiplyExtended) {
-            ASSERT_FALSE("half-precision option unimplemented");
+            ASSERT(false && "half-precision option unimplemented");
         }
 
         if (extra_behavior == ExtraBehavior::Subtract) {

src/dynarmic/src/dynarmic/ir/ir_emitter.h

@@ -124,7 +124,7 @@ public:
             ASSERT(value.GetType() == Type::U64);
             return value;
         }
-        ASSERT_FALSE("Invalid bitsize");
+        ASSERT(false && "Invalid bitsize");
     }
 
     U32 LeastSignificantWord(const U64& value) {

src/dynarmic/tests/A32/fuzz_arm.cpp

@@ -282,7 +282,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
             } else if (bitstring.substr(0, 8) == "11110100") {
                 bitstring.replace(0, 8, "11111001");
             } else {
-                ASSERT_FALSE("Unhandled ASIMD instruction: {} {}", fn, bs);
+                ASSERT(false && "Unhandled ASIMD instruction: {} {}", fn, bs);
             }
             if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
                 invalid.emplace_back(InstructionGenerator{bitstring.c_str()});

src/dynarmic/tests/test_generator.cpp

@@ -306,7 +306,7 @@ std::vector<u16> GenRandomThumbInst(u32 pc, bool is_last_inst, A32::ITState it_s
             } else if (bitstring.substr(0, 8) == "11110100") {
                 bitstring.replace(0, 8, "11111001");
             } else {
-                ASSERT_FALSE("Unhandled ASIMD instruction: {} {}", fn, bs);
+                ASSERT(false && "Unhandled ASIMD instruction: {} {}", fn, bs);
             }
             if (std::find(do_not_test.begin(), do_not_test.end(), fn) != do_not_test.end()) {
                 invalid.emplace_back(InstructionGenerator{bitstring.c_str()});