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@ -18,11 +18,35 @@ namespace Vulkan { |
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using Maxwell = Tegra::Engines::Maxwell3D::Regs; |
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struct DynamicFeatures { |
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// VK_EXT_extended_dynamic_state (EDS1) - All-or-nothing |
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bool has_extended_dynamic_state; |
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bool has_extended_dynamic_state_2; |
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bool has_extended_dynamic_state_2_extra; |
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bool has_extended_dynamic_state_3_blend; |
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bool has_extended_dynamic_state_3_enables; |
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// VK_EXT_extended_dynamic_state2 (EDS2) - Granular features |
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bool has_extended_dynamic_state_2; // Core EDS2 (RasterizerDiscard, DepthBias, PrimitiveRestart) |
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bool has_extended_dynamic_state_2_logic_op; // LogicOp support |
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bool has_extended_dynamic_state_2_patch_control_points; // TessellationPatchControlPoints |
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// VK_EXT_extended_dynamic_state3 (EDS3) - Highly granular features |
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bool has_extended_dynamic_state_3_blend; // ColorBlendEnable + ColorBlendEquation + ColorWriteMask |
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bool has_extended_dynamic_state_3_enables; // DepthClampEnable + LogicOpEnable |
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bool has_extended_dynamic_state_3_depth_clamp; // DepthClampEnable only |
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bool has_extended_dynamic_state_3_logic_op_enable; // LogicOpEnable only |
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bool has_extended_dynamic_state_3_tessellation_domain_origin; // TessellationDomainOrigin |
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bool has_extended_dynamic_state_3_polygon_mode; // PolygonMode |
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bool has_extended_dynamic_state_3_rasterization_samples; // RasterizationSamples |
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bool has_extended_dynamic_state_3_sample_mask; // SampleMask |
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bool has_extended_dynamic_state_3_alpha_to_coverage_enable; // AlphaToCoverageEnable |
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bool has_extended_dynamic_state_3_alpha_to_one_enable; // AlphaToOneEnable |
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bool has_extended_dynamic_state_3_depth_clip_enable; // DepthClipEnable |
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bool has_extended_dynamic_state_3_depth_clip_negative_one_to_one; // DepthClipNegativeOneToOne |
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bool has_extended_dynamic_state_3_line_rasterization_mode; // LineRasterizationMode |
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bool has_extended_dynamic_state_3_line_stipple_enable; // LineStippleEnable |
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bool has_extended_dynamic_state_3_provoking_vertex_mode; // ProvokingVertexMode |
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bool has_extended_dynamic_state_3_conservative_rasterization_mode; // ConservativeRasterizationMode |
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bool has_extended_dynamic_state_3_sample_locations_enable; // SampleLocationsEnable |
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bool has_extended_dynamic_state_3_rasterization_stream; // RasterizationStream |
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// VK_EXT_vertex_input_dynamic_state |
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bool has_dynamic_vertex_input; |
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}; |
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@ -184,23 +208,56 @@ struct FixedPipelineState { |
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union { |
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u32 raw1; |
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// EDS1 - Bit 0 |
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BitField<0, 1, u32> extended_dynamic_state; |
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BitField<1, 1, u32> extended_dynamic_state_2; |
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BitField<2, 1, u32> extended_dynamic_state_2_extra; |
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BitField<3, 1, u32> extended_dynamic_state_3_blend; |
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BitField<4, 1, u32> extended_dynamic_state_3_enables; |
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BitField<5, 1, u32> dynamic_vertex_input; |
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BitField<6, 1, u32> xfb_enabled; |
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BitField<7, 1, u32> ndc_minus_one_to_one; |
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BitField<8, 2, u32> polygon_mode; |
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BitField<10, 2, u32> tessellation_primitive; |
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BitField<12, 2, u32> tessellation_spacing; |
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BitField<14, 1, u32> tessellation_clockwise; |
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BitField<15, 5, u32> patch_control_points_minus_one; |
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// EDS2 - Bits 1-3 |
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BitField<1, 1, u32> extended_dynamic_state_2; |
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BitField<2, 1, u32> extended_dynamic_state_2_logic_op; |
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BitField<3, 1, u32> extended_dynamic_state_2_patch_control_points; |
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// EDS3 Blending/Enables - Bits 4-5 |
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BitField<4, 1, u32> extended_dynamic_state_3_blend; |
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BitField<5, 1, u32> extended_dynamic_state_3_enables; |
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// Vertex Input - Bit 6 |
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BitField<6, 1, u32> dynamic_vertex_input; |
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// Other state - Bits 7-19 |
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BitField<7, 1, u32> xfb_enabled; |
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BitField<8, 1, u32> ndc_minus_one_to_one; |
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BitField<9, 2, u32> polygon_mode; |
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BitField<11, 2, u32> tessellation_primitive; |
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BitField<13, 2, u32> tessellation_spacing; |
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BitField<15, 1, u32> tessellation_clockwise; |
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BitField<16, 5, u32> patch_control_points_minus_one; |
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// Topology and MSAA - Bits 24-31 |
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BitField<24, 4, Maxwell::PrimitiveTopology> topology; |
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BitField<28, 4, Tegra::Texture::MsaaMode> msaa_mode; |
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}; |
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union { |
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u32 raw1_eds3_extended; |
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// EDS3 Additional Features - Bits 0-15 |
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BitField<0, 1, u32> extended_dynamic_state_3_depth_clamp; |
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BitField<1, 1, u32> extended_dynamic_state_3_logic_op_enable; |
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BitField<2, 1, u32> extended_dynamic_state_3_tessellation_domain_origin; |
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BitField<3, 1, u32> extended_dynamic_state_3_polygon_mode; |
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BitField<4, 1, u32> extended_dynamic_state_3_rasterization_samples; |
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BitField<5, 1, u32> extended_dynamic_state_3_sample_mask; |
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BitField<6, 1, u32> extended_dynamic_state_3_alpha_to_coverage_enable; |
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BitField<7, 1, u32> extended_dynamic_state_3_alpha_to_one_enable; |
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BitField<8, 1, u32> extended_dynamic_state_3_depth_clip_enable; |
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BitField<9, 1, u32> extended_dynamic_state_3_depth_clip_negative_one_to_one; |
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BitField<10, 1, u32> extended_dynamic_state_3_line_rasterization_mode; |
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BitField<11, 1, u32> extended_dynamic_state_3_line_stipple_enable; |
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BitField<12, 1, u32> extended_dynamic_state_3_provoking_vertex_mode; |
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BitField<13, 1, u32> extended_dynamic_state_3_conservative_rasterization_mode; |
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BitField<14, 1, u32> extended_dynamic_state_3_sample_locations_enable; |
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BitField<15, 1, u32> extended_dynamic_state_3_rasterization_stream; |
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}; |
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union { |
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u32 raw2; |
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BitField<1, 3, u32> alpha_test_func; |
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