Experimental: Attempt to fix PR#180 without fully reverting vk_scheduler.cpp to old logic.

This is an experiment. This tries to retain the EndRenderPass() logic while attempting to fix final fantasy tactics for AMD+Windows.
PR#3069 fully reverts the logic to fix the regression. Does this work? Is this a better way?

src/video_core/renderer_vulkan/vk_scheduler.cpp

@@ -270,8 +270,7 @@ void Scheduler::EndPendingOperations() {
     EndRenderPass();
 }
 
-void Scheduler::EndRenderPass()
-    {
+void Scheduler::EndRenderPass() {
     if (!state.renderpass) {
         return;
     }
@@ -287,10 +286,9 @@ void Scheduler::EndRenderPass()
 
         for (size_t i = 0; i < num_images; ++i) {
             const VkImageSubresourceRange& range = ranges[i];
-                const bool is_color = range.aspectMask & VK_IMAGE_ASPECT_COLOR_BIT;
-                const bool is_depth_stencil = range.aspectMask
-                                              & (VK_IMAGE_ASPECT_DEPTH_BIT
-                                                 | VK_IMAGE_ASPECT_STENCIL_BIT);
+            const bool is_color = (range.aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) != 0;
+            const bool is_depth_stencil = (range.aspectMask &
+                                           (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) != 0;
 
             VkAccessFlags src_access = 0;
             VkPipelineStageFlags this_stage = 0;
@@ -302,8 +300,8 @@ void Scheduler::EndRenderPass()
 
             if (is_depth_stencil) {
                 src_access |= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
-                    this_stage |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT
-                                  | VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT;
+                this_stage |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
+                              VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT;
             }
 
             src_stages |= this_stage;
@@ -312,11 +310,9 @@ void Scheduler::EndRenderPass()
                 .sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER,
                 .pNext = nullptr,
                 .srcAccessMask = src_access,
-                        .dstAccessMask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT
-                                         | VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
-                                         | VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
-                                         | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
-                                         | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
+                .dstAccessMask = VK_ACCESS_SHADER_READ_BIT | VK_ACCESS_SHADER_WRITE_BIT |
+                                 VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT |
+                                 VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
                 .oldLayout = VK_IMAGE_LAYOUT_GENERAL,
                 .newLayout = VK_IMAGE_LAYOUT_GENERAL,
                 .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
@@ -326,14 +322,20 @@ void Scheduler::EndRenderPass()
             };
         }
 
+        // Graft: ensure explicit fragment tests + color output stages are always synchronized (AMD/Windows fix)
+        src_stages |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
+                      VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
+                      VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
+
         cmdbuf.EndRenderPass();
 
-            cmdbuf.PipelineBarrier(src_stages,
+        cmdbuf.PipelineBarrier(
+            src_stages,
             VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
             0,
-                                   {},
-                                   {},
-                                   {barriers.data(), num_images} // Batched image barriers
+            nullptr,
+            nullptr,
+            vk::Span(barriers.data(), num_images)  // Batched image barriers
         );
     });