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@ -86,6 +86,26 @@ public: |
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num_instructions, MemoryReadCode(pc)); |
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} |
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void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op, |
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VAddr value) override { |
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switch (op) { |
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case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: { |
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static constexpr u64 ICACHE_LINE_SIZE = 64; |
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); |
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parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); |
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break; |
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} |
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: |
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parent.ClearInstructionCache(); |
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break; |
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: |
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default: |
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LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op); |
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break; |
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} |
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} |
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { |
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switch (exception) { |
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case Dynarmic::A64::Exception::WaitForInterrupt: |
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