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@ -45,6 +45,8 @@ NvResult nvhost_ctrl_gpu::Ioctl1(DeviceFD fd, Ioctl command, std::span<const u8> |
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return WrapFixed(this, &nvhost_ctrl_gpu::GetActiveSlotMask, input, output); |
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return WrapFixed(this, &nvhost_ctrl_gpu::GetActiveSlotMask, input, output); |
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case 0x1c: |
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case 0x1c: |
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return WrapFixed(this, &nvhost_ctrl_gpu::GetGpuTime, input, output); |
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return WrapFixed(this, &nvhost_ctrl_gpu::GetGpuTime, input, output); |
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case 0x13: |
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return WrapFixed(this, &nvhost_ctrl_gpu::GetTpcMasks2, input, output); |
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default: |
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default: |
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break; |
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break; |
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} |
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} |
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@ -71,6 +73,23 @@ NvResult nvhost_ctrl_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8> |
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case 0x6: |
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case 0x6: |
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return WrapFixedInlOut(this, &nvhost_ctrl_gpu::GetTPCMasks3, input, output, |
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return WrapFixedInlOut(this, &nvhost_ctrl_gpu::GetTPCMasks3, input, output, |
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inline_output); |
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inline_output); |
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case 0x13: { |
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// NVGPU_GPU_IOCTL_NUM_VSMS
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struct Parameters { |
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u32 num_vsms; // Output: number of SM units
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u32 reserved; // Output: reserved/padding
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}; |
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static_assert(sizeof(Parameters) == 8, "Parameters is incorrect size"); |
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// The Tegra X1 used in Switch has 2 SM units
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Parameters params{ |
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.num_vsms = 2, |
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.reserved = 0 |
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}; |
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std::memcpy(output.data(), ¶ms, sizeof(Parameters)); |
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return NvResult::Success; |
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} |
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default: |
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default: |
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break; |
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break; |
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} |
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} |
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@ -78,7 +97,8 @@ NvResult nvhost_ctrl_gpu::Ioctl3(DeviceFD fd, Ioctl command, std::span<const u8> |
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default: |
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default: |
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break; |
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break; |
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} |
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} |
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UNIMPLEMENTED_MSG("Unimplemented ioctl={:08X}", command.raw); |
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UNIMPLEMENTED_MSG("Unimplemented ioctl={:08X}, group={:01X}, command={:01X}", command.raw, |
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command.group, command.cmd); |
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return NvResult::NotImplemented; |
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return NvResult::NotImplemented; |
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} |
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} |
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