dynarmic: Update to 41ae12263

Changes: Primarily implementing more A64 instructions

.travis/macos/build.sh

@@ -2,7 +2,7 @@
 
 set -o pipefail
 
-export MACOSX_DEPLOYMENT_TARGET=10.9
+export MACOSX_DEPLOYMENT_TARGET=10.12
 export Qt5_DIR=$(brew --prefix)/opt/qt5
 export UNICORNDIR=$(pwd)/externals/unicorn
 

externals/dynarmic

@@ -1 +1 @@
-Subproject commit a6d17e6bb0ffd16464b7dae8c1124b0c6a742a15
+Subproject commit 41ae12263da7c6d1ffafec6a5b9095977b42367d

externals/xbyak

@@ -1 +1 @@
-Subproject commit d512551e914737300ba35f3c049d1b40effbe76d
+Subproject commit 2794cde79eb71e86490061cac9622ad0067b8d15

src/core/arm/dynarmic/arm_dynarmic.cpp

@@ -8,9 +8,12 @@
 #include <dynarmic/A64/config.h>
 #include "core/arm/dynarmic/arm_dynarmic.h"
 #include "core/core_timing.h"
+#include "core/hle/kernel/memory.h"
 #include "core/hle/kernel/svc.h"
 #include "core/memory.h"
 
+using Vector = Dynarmic::A64::Vector;
+
 class ARM_Dynarmic_Callbacks : public Dynarmic::A64::UserCallbacks {
 public:
     explicit ARM_Dynarmic_Callbacks(ARM_Dynarmic& parent) : parent(parent) {}
@@ -28,6 +31,9 @@ public:
     u64 MemoryRead64(u64 vaddr) override {
         return Memory::Read64(vaddr);
     }
+    Vector MemoryRead128(u64 vaddr) override {
+        return {Memory::Read64(vaddr), Memory::Read64(vaddr + 8)};
+    }
 
     void MemoryWrite8(u64 vaddr, u8 value) override {
         Memory::Write8(vaddr, value);
@@ -41,6 +47,10 @@ public:
     void MemoryWrite64(u64 vaddr, u64 value) override {
         Memory::Write64(vaddr, value);
     }
+    void MemoryWrite128(u64 vaddr, Vector value) override {
+        Memory::Write64(vaddr, value[0]);
+        Memory::Write64(vaddr + 8, value[1]);
+    }
 
     void InterpreterFallback(u64 pc, size_t num_instructions) override {
         ARM_Interface::ThreadContext ctx;
@@ -52,12 +62,12 @@ public:
         num_interpreted_instructions += num_instructions;
     }
 
-    void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override {
-        ASSERT_MSG(false, "ExceptionRaised(%" PRIx64 ")", pc);
+    void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
+        ASSERT_MSG(false, "ExceptionRaised(exception = %zu, pc = %" PRIx64 ")",
+                   static_cast<size_t>(exception), pc);
     }
 
     void CallSVC(u32 swi) override {
-        printf("svc %x\n", swi);
         Kernel::CallSVC(swi);
     }
 
@@ -78,9 +88,13 @@ public:
     u64 tpidrr0_el0 = 0;
 };
 
+std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_Callbacks>& cb) {
+    Dynarmic::A64::UserConfig config{cb.get()};
+    return std::make_unique<Dynarmic::A64::Jit>(config);
+}
+
 ARM_Dynarmic::ARM_Dynarmic()
-    : cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)),
-      jit(Dynarmic::A64::UserConfig{cb.get()}) {
+    : cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), jit(MakeJit(cb)) {
     ARM_Interface::ThreadContext ctx;
     inner_unicorn.SaveContext(ctx);
     LoadContext(ctx);
@@ -94,27 +108,27 @@ void ARM_Dynarmic::MapBackingMemory(u64 address, size_t size, u8* memory,
 }
 
 void ARM_Dynarmic::SetPC(u64 pc) {
-    jit.SetPC(pc);
+    jit->SetPC(pc);
 }
 
 u64 ARM_Dynarmic::GetPC() const {
-    return jit.GetPC();
+    return jit->GetPC();
 }
 
 u64 ARM_Dynarmic::GetReg(int index) const {
-    return jit.GetRegister(index);
+    return jit->GetRegister(index);
 }
 
 void ARM_Dynarmic::SetReg(int index, u64 value) {
-    jit.SetRegister(index, value);
+    jit->SetRegister(index, value);
 }
 
 u128 ARM_Dynarmic::GetExtReg(int index) const {
-    return jit.GetVector(index);
+    return jit->GetVector(index);
 }
 
 void ARM_Dynarmic::SetExtReg(int index, u128 value) {
-    jit.SetVector(index, value);
+    jit->SetVector(index, value);
 }
 
 u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const {
@@ -127,11 +141,11 @@ void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) {
 }
 
 u32 ARM_Dynarmic::GetCPSR() const {
-    return jit.GetPstate();
+    return jit->GetPstate();
 }
 
 void ARM_Dynarmic::SetCPSR(u32 cpsr) {
-    jit.SetPstate(cpsr);
+    jit->SetPstate(cpsr);
 }
 
 u64 ARM_Dynarmic::GetTlsAddress() const {
@@ -144,41 +158,41 @@ void ARM_Dynarmic::SetTlsAddress(u64 address) {
 
 void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
     cb->ticks_remaining = num_instructions;
-    jit.Run();
+    jit->Run();
     CoreTiming::AddTicks(num_instructions - cb->num_interpreted_instructions);
     cb->num_interpreted_instructions = 0;
 }
 
 void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
-    ctx.cpu_registers = jit.GetRegisters();
-    ctx.sp = jit.GetSP();
-    ctx.pc = jit.GetPC();
-    ctx.cpsr = jit.GetPstate();
-    ctx.fpu_registers = jit.GetVectors();
-    ctx.fpscr = jit.GetFpcr();
+    ctx.cpu_registers = jit->GetRegisters();
+    ctx.sp = jit->GetSP();
+    ctx.pc = jit->GetPC();
+    ctx.cpsr = jit->GetPstate();
+    ctx.fpu_registers = jit->GetVectors();
+    ctx.fpscr = jit->GetFpcr();
     ctx.tls_address = cb->tpidrr0_el0;
 }
 
 void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
-    jit.SetRegisters(ctx.cpu_registers);
-    jit.SetSP(ctx.sp);
-    jit.SetPC(ctx.pc);
-    jit.SetPstate(static_cast<u32>(ctx.cpsr));
-    jit.SetVectors(ctx.fpu_registers);
-    jit.SetFpcr(static_cast<u32>(ctx.fpscr));
+    jit->SetRegisters(ctx.cpu_registers);
+    jit->SetSP(ctx.sp);
+    jit->SetPC(ctx.pc);
+    jit->SetPstate(static_cast<u32>(ctx.cpsr));
+    jit->SetVectors(ctx.fpu_registers);
+    jit->SetFpcr(static_cast<u32>(ctx.fpscr));
     cb->tpidrr0_el0 = ctx.tls_address;
 }
 
 void ARM_Dynarmic::PrepareReschedule() {
-    if (jit.IsExecuting()) {
-        jit.HaltExecution();
+    if (jit->IsExecuting()) {
+        jit->HaltExecution();
     }
 }
 
 void ARM_Dynarmic::ClearInstructionCache() {
-    jit.ClearCache();
+    jit->ClearCache();
 }
 
 void ARM_Dynarmic::PageTableChanged() {
-    UNIMPLEMENTED();
+    jit = MakeJit(cb);
 }

src/core/arm/dynarmic/arm_dynarmic.h

@@ -45,6 +45,6 @@ public:
 private:
     friend class ARM_Dynarmic_Callbacks;
     std::unique_ptr<ARM_Dynarmic_Callbacks> cb;
-    Dynarmic::A64::Jit jit;
+    std::unique_ptr<Dynarmic::A64::Jit> jit;
     ARM_Unicorn inner_unicorn;
 };