Exverge
1 month ago
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7 changed files with 140 additions and 270 deletions
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33src/common/assert.h
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2src/core/CMakeLists.txt
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140src/core/arm/nce/arm_nce.cpp
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5src/core/arm/nce/arm_nce.h
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189src/core/arm/nce/arm_nce.s
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40src/core/arm/nce/arm_nce_asm_definitions.h
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1src/core/arm/nce/guest_context.h
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/* SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project */ |
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/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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#define __ASSEMBLY__ |
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#include "core/arm/nce/arm_nce_asm_definitions.h" |
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#define LOAD_IMMEDIATE_32(reg, val) \ |
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mov reg, #(((val) >> 0x00) & 0xFFFF); \ |
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movk reg, #(((val) >> 0x10) & 0xFFFF), lsl #16 |
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#ifdef __APPLE__ |
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#define SYM(name) _##name |
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.macro ASM_FUNCTION_START name |
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.text |
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.align 2 |
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.global _\name |
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_\name: |
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.endm |
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#else |
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#define SYM(name) name |
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.macro ASM_FUNCTION_START name |
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.section .text.\name, "ax", %progbits |
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.global \name |
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.type \name, %function |
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\name: |
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.endm |
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#endif |
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/* static HaltReason Core::ArmNce::ReturnToRunCodeByTrampoline(void* tpidr, Core::GuestContext* ctx, u64 trampoline_addr) */ |
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#ifndef __APPLE__ |
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ASM_FUNCTION_START _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEm |
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#else |
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ASM_FUNCTION_START _ZN4Core6ArmNce27ReturnToRunCodeByTrampolineEPvPNS_12GuestContextEy |
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#endif |
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/* Back up host sp to x3. */ |
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/* Back up host tpidr_el0 to x4. */ |
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mov x3, sp |
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mrs x4, tpidr_el0 |
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/* Load guest sp. x5 is used as a scratch register. */ |
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ldr x5, [x1, #(GuestContextSp)] |
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mov sp, x5 |
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/* Offset GuestContext pointer to the host member. */ |
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add x5, x1, #(GuestContextHostContext) |
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/* Save original host sp and tpidr_el0 (x3, x4) to host context. */ |
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stp x3, x4, [x5, #(HostContextSpTpidrEl0)] |
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/* Save all callee-saved host GPRs. */ |
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stp x19, x20, [x5, #(HostContextRegs+0x0)] |
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stp x21, x22, [x5, #(HostContextRegs+0x10)] |
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stp x23, x24, [x5, #(HostContextRegs+0x20)] |
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stp x25, x26, [x5, #(HostContextRegs+0x30)] |
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stp x27, x28, [x5, #(HostContextRegs+0x40)] |
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stp x29, x30, [x5, #(HostContextRegs+0x50)] |
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/* Save all callee-saved host FPRs. */ |
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stp q8, q9, [x5, #(HostContextVregs+0x0)] |
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stp q10, q11, [x5, #(HostContextVregs+0x20)] |
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stp q12, q13, [x5, #(HostContextVregs+0x40)] |
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stp q14, q15, [x5, #(HostContextVregs+0x60)] |
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/* Load guest tpidr_el0 from argument. */ |
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msr tpidr_el0, x0 |
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/* Tail call the trampoline to restore guest state. */ |
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br x2 |
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/* static HaltReason Core::ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void* tpidr) */ |
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ASM_FUNCTION_START _ZN4Core6ArmNce37ReturnToRunCodeByExceptionLevelChangeEiPv |
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/* This jumps to the signal handler, which will restore the entire context. */ |
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/* On entry, x0 = thread id, which is already in the right place. */ |
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/* Move tpidr to x9 so it is not trampled. */ |
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mov x9, x1 |
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/* Set up arguments. */ |
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/* On entry, x0 = thread id, which is already in the right place. */ |
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mov x1, #(ReturnToRunCodeByExceptionLevelChangeSignal) |
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/* Tail call the signal handler. */ |
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#ifndef __APPLE__ |
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mov x8, #(__NR_tkill) |
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svc #0 |
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#else |
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mov x16, #(__pthread_pkill) |
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svc #0x80 |
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#endif |
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/* Block execution from flowing here. */ |
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brk #1000 |
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/* static void Core::ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void* info, void* raw_context) */ |
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ASM_FUNCTION_START _ZN4Core6ArmNce50ReturnToRunCodeByExceptionLevelChangeSignalHandlerEiPvS1_ |
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stp x29, x30, [sp, #-0x10]! |
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mov x29, sp |
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/* Call the context restorer with the raw context. */ |
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mov x0, x2 |
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bl SYM(_ZN4Core6ArmNce19RestoreGuestContextEPv) |
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/* Save the old value of tpidr_el0. */ |
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mrs x8, tpidr_el0 |
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ldr x9, [x0, #(TpidrEl0NativeContext)] |
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str x8, [x9, #(GuestContextHostContext + HostContextTpidrEl0)] |
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/* Set our new tpidr_el0. */ |
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msr tpidr_el0, x0 |
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/* Unlock the context. */ |
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bl SYM(_ZN4Core6ArmNce22UnlockThreadParametersEPv) |
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/* Returning from here will enter the guest. */ |
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ldp x29, x30, [sp], #0x10 |
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ret |
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/* static void Core::ArmNce::BreakFromRunCodeSignalHandler(int sig, void* info, void* raw_context) */ |
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ASM_FUNCTION_START _ZN4Core6ArmNce29BreakFromRunCodeSignalHandlerEiPvS1_ |
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/* Check to see if we have the correct TLS magic. */ |
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mrs x8, tpidr_el0 |
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ldr w9, [x8, #(TpidrEl0TlsMagic)] |
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LOAD_IMMEDIATE_32(w10, TlsMagic) |
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cmp w9, w10 |
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b.ne 1f |
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/* Correct TLS magic, so this is a guest interrupt. */ |
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/* Restore host tpidr_el0. */ |
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ldr x0, [x8, #(TpidrEl0NativeContext)] |
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ldr x3, [x0, #(GuestContextHostContext + HostContextTpidrEl0)] |
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msr tpidr_el0, x3 |
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/* Tail call the restorer. */ |
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mov x1, x2 |
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b SYM(_ZN4Core6ArmNce16SaveGuestContextEPNS_12GuestContextEPv) |
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/* Returning from here will enter host code. */ |
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1: |
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/* Incorrect TLS magic, so this is a spurious signal. */ |
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ret |
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/* static void Core::ArmNce::LockThreadParameters(void* tpidr) */ |
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ASM_FUNCTION_START _ZN4Core6ArmNce20LockThreadParametersEPv |
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/* Offset to lock member. */ |
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add x0, x0, #(TpidrEl0Lock) |
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1: |
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/* Clear the monitor. */ |
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clrex |
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2: |
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/* Load-linked with acquire ordering. */ |
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ldaxr w1, [x0] |
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/* If the value was SpinLockLocked, clear monitor and retry. */ |
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cbz w1, 1b |
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/* Store-conditional SpinLockLocked with relaxed ordering. */ |
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stxr w1, wzr, [x0] |
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/* If we failed to store, retry. */ |
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cbnz w1, 2b |
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ret |
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/* static void Core::ArmNce::UnlockThreadParameters(void* tpidr) */ |
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ASM_FUNCTION_START _ZN4Core6ArmNce22UnlockThreadParametersEPv |
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/* Offset to lock member. */ |
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add x0, x0, #(TpidrEl0Lock) |
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/* Load SpinLockUnlocked. */ |
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mov w1, #(SpinLockUnlocked) |
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/* Store value with release ordering. */ |
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stlr w1, [x0] |
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ret |
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@ -1,40 +0,0 @@ |
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// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project |
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// SPDX-License-Identifier: GPL-3.0-or-later |
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// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project |
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// SPDX-License-Identifier: GPL-2.0-or-later |
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#pragma once |
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#if defined(__ASSEMBLY__) && defined(__linux__) |
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#include <asm-generic/signal.h> |
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#include <asm-generic/unistd.h> |
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#else |
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#define SIGUSR2 31 |
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#define SIGURG 16 |
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#define SIGSEGV 11 |
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#define SIGBUS 10 |
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#define __pthread_pkill 328 |
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#endif |
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#define ReturnToRunCodeByExceptionLevelChangeSignal SIGUSR2 |
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#define BreakFromRunCodeSignal SIGURG |
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#define GuestAccessFaultSignal SIGSEGV |
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#define GuestAlignmentFaultSignal SIGBUS |
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#define GuestContextSp 0xF8 |
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#define GuestContextHostContext 0x320 |
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#define HostContextSpTpidrEl0 0xE0 |
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#define HostContextTpidrEl0 0xE8 |
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#define HostContextRegs 0x0 |
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#define HostContextVregs 0x60 |
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#define TpidrEl0NativeContext 0x10 |
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#define TpidrEl0Lock 0x18 |
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#define TpidrEl0TlsMagic 0x20 |
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#define TlsMagic 0x555a5559 |
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#define SpinLockLocked 0 |
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#define SpinLockUnlocked 1 |
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