i should test my code

src/core/arm/nce/arm_nce.cpp

@@ -470,13 +470,17 @@ void ArmNce::SignalInterrupt(Kernel::KThread* thread) {
     }
 }
 
-void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
+void ArmNce::ClearInstructionCache() {
     // Ensure all previous memory operations complete
     asm volatile("dsb ish\n"
                  "dsb ish\n"
                  "isb" ::: "memory");
 }
 
+void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
+    ClearInstructionCache();
+}
+
 } // namespace Core
 
 #endif // #ifdef __aarch64__

src/core/arm/nce/arm_nce.h

@@ -52,6 +52,7 @@ public:
 
     void SignalInterrupt(Kernel::KThread* thread) override;
     void InvalidateCacheRange(u64 addr, std::size_t size) override;
+    void ClearInstructionCache() override;
 
     void LockThread(Kernel::KThread* thread) override;
     void UnlockThread(Kernel::KThread* thread) override;