dyncom: Handle the ARM A2 encoding of STRT/LDRT

These were also missing the shifted register case.

src/core/arm/dyncom/arm_dyncom_interpreter.cpp

@@ -1848,9 +1848,16 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index)
     inst_base->br   = NON_BRANCH;
 
     inst_cream->inst = inst;
-    if (I_BIT == 0) {
+    if (BITS(inst, 25, 27) == 2) {
         inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
+    } else if (BITS(inst, 25, 27) == 3) {
+        inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
     } else {
+        // Reaching this would indicate the thumb version
+        // of this instruction, however the 3DS CPU doesn't
+        // support this variant (the 3DS CPU is only ARMv6K,
+        // while this variant is added in ARMv6T2).
+        // So it's sufficient for citra to not implement this.
         DEBUG_MSG;
     }
 
@@ -2800,9 +2807,16 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index)
     inst_base->br   = NON_BRANCH;
 
     inst_cream->inst = inst;
-    if (I_BIT == 0) {
+    if (BITS(inst, 25, 27) == 2) {
         inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed);
+    } else if (BITS(inst, 25, 27) == 3) {
+        inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed);
     } else {
+        // Reaching this would indicate the thumb version
+        // of this instruction, however the 3DS CPU doesn't
+        // support this variant (the 3DS CPU is only ARMv6K,
+        // while this variant is added in ARMv6T2).
+        // So it's sufficient for citra to not implement this.
         DEBUG_MSG;
     }