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@ -97,6 +97,26 @@ void EmitShuffleButterfly(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, Sca |
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Shuffle(ctx, inst, value, index, clamp, segmentation_mask, "XOR"); |
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} |
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void EmitQuadBroadcast(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 lane) { |
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// QuadBroadcast: src = (thread_id & ~3) | (lane & 3) — SHFLIDX with quad mask 0x1C03
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const Register ret{ctx.reg_alloc.Define(inst)}; |
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ctx.Add("AND.U RC.x,{}.threadid,~3;" |
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"AND.U RC.y,{},3;" |
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"OR.U RC.x,RC.x,RC.y;" |
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"SHFLIDX.U {},{},RC.x,0x1C03;" |
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"MOV.U {}.x,{}.x;", |
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ctx.stage_name, lane, ret, value, ret, ret); |
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} |
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void EmitQuadSwap(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 direction) { |
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// QuadSwap: XOR thread_id with (direction+1) within quad — SHFLXOR with quad mask 0x1C03
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const Register ret{ctx.reg_alloc.Define(inst)}; |
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ctx.Add("ADD.U RC.x,{},1;" |
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"SHFLXOR.U {},{},RC.x,0x1C03;" |
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"MOV.U {}.x,{}.x;", |
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direction, ret, value, ret, ret); |
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} |
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void EmitFSwizzleAdd(EmitContext& ctx, IR::Inst& inst, ScalarF32 op_a, ScalarF32 op_b, |
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ScalarU32 swizzle) { |
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const auto ret{ctx.reg_alloc.Define(inst)}; |
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