[spir-v] Early stage quad control implementation

src/shader_recompiler/backend/spirv/emit_spirv.cpp

@@ -322,6 +322,11 @@ void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
         if (ctx.runtime_info.force_early_z) {
             ctx.AddExecutionMode(main, spv::ExecutionMode::EarlyFragmentTests);
         }
+        if (ctx.profile.support_shader_quad_control && program.info.uses_derivatives) {
+            ctx.AddExtension("SPV_KHR_quad_control");
+            ctx.AddCapability(spv::Capability::QuadControlKHR);
+            ctx.AddExecutionMode(main, spv::ExecutionMode::RequireFullQuadsKHR);
+        }
         break;
     default:
         throw NotImplementedException("Stage {}", program.stage);
@@ -440,6 +445,9 @@ void SetupCapabilities(const Profile& profile, const Info& info, EmitContext& ct
             ctx.AddCapability(spv::Capability::GroupNonUniformVote);
         }
     }
+    if (info.uses_quad_shuffles && profile.support_quad_shuffles) {
+        ctx.AddCapability(spv::Capability::GroupNonUniformQuad);
+    }
     if (info.uses_int64_bit_atomics && profile.support_int64_atomics) {
         ctx.AddCapability(spv::Capability::Int64Atomics);
     }

src/shader_recompiler/backend/spirv/emit_spirv_instructions.h

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
@@ -622,6 +622,8 @@ Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clam
                    Id segmentation_mask);
 Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
                         Id segmentation_mask);
+Id EmitQuadBroadcast(EmitContext& ctx, Id value, Id lane);
+Id EmitQuadSwap(EmitContext& ctx, Id value, Id direction);
 Id EmitFSwizzleAdd(EmitContext& ctx, Id op_a, Id op_b, Id swizzle);
 Id EmitDPdxFine(EmitContext& ctx, Id op_a);
 Id EmitDPdyFine(EmitContext& ctx, Id op_a);

src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
@@ -220,6 +223,14 @@ Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id
     return SelectValue(ctx, in_range, value, src_thread_id);
 }
 
+Id EmitQuadBroadcast(EmitContext& ctx, Id value, Id lane) {
+    return ctx.OpGroupNonUniformQuadBroadcast(ctx.U32[1], SubgroupScope(ctx), value, lane);
+}
+
+Id EmitQuadSwap(EmitContext& ctx, Id value, Id direction) {
+    return ctx.OpGroupNonUniformQuadSwap(ctx.U32[1], SubgroupScope(ctx), value, direction);
+}
+
 Id EmitFSwizzleAdd(EmitContext& ctx, Id op_a, Id op_b, Id swizzle) {
     const Id three{ctx.Const(3U)};
     Id mask{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};

src/shader_recompiler/frontend/ir/ir_emitter.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
@@ -2100,6 +2100,14 @@ U32 IREmitter::ShuffleButterfly(const IR::U32& value, const IR::U32& index, cons
     return Inst<U32>(Opcode::ShuffleButterfly, value, index, clamp, seg_mask);
 }
 
+U32 IREmitter::QuadBroadcast(const IR::U32& value, const IR::U32& lane) {
+    return Inst<U32>(Opcode::QuadBroadcast, value, lane);
+}
+
+U32 IREmitter::QuadSwap(const IR::U32& value, const IR::U32& direction) {
+    return Inst<U32>(Opcode::QuadSwap, value, direction);
+}
+
 F32 IREmitter::FSwizzleAdd(const F32& a, const F32& b, const U32& swizzle, FpControl control) {
     return Inst<F32>(Opcode::FSwizzleAdd, Flags{control}, a, b, swizzle);
 }

src/shader_recompiler/frontend/ir/ir_emitter.h

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
@@ -394,6 +394,8 @@ public:
                                   const IR::U32& seg_mask);
     [[nodiscard]] U32 ShuffleButterfly(const IR::U32& value, const IR::U32& index,
                                        const IR::U32& clamp, const IR::U32& seg_mask);
+    [[nodiscard]] U32 QuadBroadcast(const IR::U32& value, const IR::U32& lane);
+    [[nodiscard]] U32 QuadSwap(const IR::U32& value, const IR::U32& direction);
     [[nodiscard]] F32 FSwizzleAdd(const F32& a, const F32& b, const U32& swizzle,
                                   FpControl control = {});
 

src/shader_recompiler/frontend/ir/opcodes.inc

@@ -1,3 +1,6 @@
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
+// SPDX-License-Identifier: GPL-3.0-or-later
+
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
 
@@ -579,6 +582,8 @@ OPCODE(ShuffleIndex,                                        U32,            U32,
 OPCODE(ShuffleUp,                                           U32,            U32,            U32,            U32,            U32,                            )
 OPCODE(ShuffleDown,                                         U32,            U32,            U32,            U32,            U32,                            )
 OPCODE(ShuffleButterfly,                                    U32,            U32,            U32,            U32,            U32,                            )
+OPCODE(QuadBroadcast,                                       U32,            U32,            U32,                                                                    )
+OPCODE(QuadSwap,                                            U32,            U32,            U32,                                                                    )
 OPCODE(FSwizzleAdd,                                         F32,            F32,            F32,            U32,                                            )
 OPCODE(DPdxFine,                                            F32,            F32,                                                                            )
 OPCODE(DPdyFine,                                            F32,            F32,                                                                            )

src/shader_recompiler/frontend/maxwell/translate/impl/warp_shuffle.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
@@ -36,7 +36,12 @@ enum class ShuffleMode : u64 {
     }
 }
 
-void Shuffle(TranslatorVisitor& v, u64 insn, const IR::U32& index, const IR::U32& mask) {
+// SHFL mask encoding for quad-constrained operations:
+// bits [0:4] = clamp = 3, bits [8:12] = seg_mask = 28 (0x1C)
+constexpr u32 QUAD_MASK = (28u << 8) | 3u; // 0x1C03
+
+void Shuffle(TranslatorVisitor& v, u64 insn, const IR::U32& index, const IR::U32& mask,
+             bool index_is_imm, u32 index_imm, bool mask_is_imm, u32 mask_imm) {
     union {
         u64 insn;
         BitField<0, 8, IR::Reg> dest_reg;
@@ -45,6 +50,21 @@ void Shuffle(TranslatorVisitor& v, u64 insn, const IR::U32& index, const IR::U32
         BitField<48, 3, IR::Pred> pred;
     } const shfl{insn};
 
+    if (mask_is_imm && mask_imm == QUAD_MASK && index_is_imm) {
+        if (shfl.mode == ShuffleMode::IDX && index_imm <= 3) {
+            // SHFL IDX with lane 0-3 in a quad → QuadBroadcast
+            v.X(shfl.dest_reg, v.ir.QuadBroadcast(v.X(shfl.src_reg), v.ir.Imm32(index_imm)));
+            v.ir.SetPred(shfl.pred, v.ir.Imm1(true));
+            return;
+        }
+        if (shfl.mode == ShuffleMode::BFLY && index_imm >= 1 && index_imm <= 3) {
+            // SHFL BFLY index 1/2/3 in a quad → QuadSwap direction 0/1/2
+            v.X(shfl.dest_reg, v.ir.QuadSwap(v.X(shfl.src_reg), v.ir.Imm32(index_imm - 1)));
+            v.ir.SetPred(shfl.pred, v.ir.Imm1(true));
+            return;
+        }
+    }
+
     const IR::U32 result{ShuffleOperation(v.ir, v.X(shfl.src_reg), index, mask, shfl.mode)};
     v.ir.SetPred(shfl.pred, v.ir.GetInBoundsFromOp(result));
     v.X(shfl.dest_reg, result);
@@ -59,11 +79,14 @@ void TranslatorVisitor::SHFL(u64 insn) {
         BitField<29, 1, u64> src_b_flag;
         BitField<34, 13, u64> src_b_imm;
     } const flags{insn};
-    const IR::U32 src_a{flags.src_a_flag != 0 ? ir.Imm32(static_cast<u32>(flags.src_a_imm))
-                                              : GetReg20(insn)};
-    const IR::U32 src_b{flags.src_b_flag != 0 ? ir.Imm32(static_cast<u32>(flags.src_b_imm))
-                                              : GetReg39(insn)};
-    Shuffle(*this, insn, src_a, src_b);
+    const bool index_is_imm{flags.src_a_flag != 0};
+    const bool mask_is_imm{flags.src_b_flag != 0};
+    const IR::U32 src_a{index_is_imm ? ir.Imm32(static_cast<u32>(flags.src_a_imm))
+                                     : GetReg20(insn)};
+    const IR::U32 src_b{mask_is_imm ? ir.Imm32(static_cast<u32>(flags.src_b_imm))
+                                    : GetReg39(insn)};
+    Shuffle(*this, insn, src_a, src_b, index_is_imm, static_cast<u32>(flags.src_a_imm),
+            mask_is_imm, static_cast<u32>(flags.src_b_imm));
 }
 
 } // namespace Shader::Maxwell

src/shader_recompiler/ir_opt/collect_shader_info_pass.cpp

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
@@ -498,6 +498,10 @@ void VisitUsages(Info& info, IR::Inst& inst) {
     case IR::Opcode::ShuffleButterfly:
         info.uses_subgroup_shuffles = true;
         break;
+    case IR::Opcode::QuadBroadcast:
+    case IR::Opcode::QuadSwap:
+        info.uses_quad_shuffles = true;
+        break;
     case IR::Opcode::GetCbufU8:
     case IR::Opcode::GetCbufS8:
     case IR::Opcode::GetCbufU16:

src/shader_recompiler/profile.h

@@ -29,6 +29,8 @@ struct Profile {
     bool support_fp32_signed_zero_nan_preserve{};
     bool support_fp64_signed_zero_nan_preserve{};
     bool support_explicit_workgroup_layout{};
+    bool support_shader_quad_control{};
+    bool support_quad_shuffles{};
     bool support_vote{};
     bool support_viewport_index_layer_non_geometry{};
     bool support_viewport_mask{};

src/shader_recompiler/shader_info.h

@@ -251,6 +251,7 @@ struct Info {
     bool uses_is_helper_invocation{};
     bool uses_subgroup_invocation_id{};
     bool uses_subgroup_shuffles{};
+    bool uses_quad_shuffles{};
     std::array<bool, 30> uses_patches{};
 
     std::array<Interpolation, 32> interpolation{};

src/video_core/renderer_vulkan/vk_pipeline_cache.cpp

@@ -402,6 +402,8 @@ PipelineCache::PipelineCache(Tegra::MaxwellDeviceMemoryManager& device_memory_,
         .support_fp64_signed_zero_nan_preserve =
             float_control.shaderSignedZeroInfNanPreserveFloat64 != VK_FALSE,
         .support_explicit_workgroup_layout = device.IsKhrWorkgroupMemoryExplicitLayoutSupported(),
+        .support_shader_quad_control = device.IsKhrShaderQuadControlSupported(),
+        .support_quad_shuffles = device.IsSubgroupFeatureSupported(VK_SUBGROUP_FEATURE_QUAD_BIT),
         .support_vote = device.IsSubgroupFeatureSupported(VK_SUBGROUP_FEATURE_VOTE_BIT),
         .support_viewport_index_layer_non_geometry =
             device.IsExtShaderViewportIndexLayerSupported(),

src/video_core/vulkan_common/vulkan_device.cpp

@@ -1330,6 +1330,11 @@ void Device::RemoveUnsuitableExtensions() {
                                VK_KHR_PIPELINE_EXECUTABLE_PROPERTIES_EXTENSION_NAME);
     }
 
+    // VK_KHR_shader_quad_control
+    extensions.shader_quad_control = features.shader_quad_control.shaderQuadControl;
+    RemoveExtensionFeatureIfUnsuitable(extensions.shader_quad_control, features.shader_quad_control,
+                                       VK_KHR_SHADER_QUAD_CONTROL_EXTENSION_NAME);
+
     // VK_KHR_workgroup_memory_explicit_layout
     extensions.workgroup_memory_explicit_layout =
         features.features.shaderInt16 &&

src/video_core/vulkan_common/vulkan_device.h

@@ -68,6 +68,7 @@ VK_DEFINE_HANDLE(VmaAllocator)
     FEATURE(KHR, Maintenance6, MAINTENANCE_6, maintenance6)                                        \
     FEATURE(KHR, PipelineExecutableProperties, PIPELINE_EXECUTABLE_PROPERTIES,                     \
             pipeline_executable_properties)                                                        \
+    FEATURE(KHR, ShaderQuadControl, SHADER_QUAD_CONTROL, shader_quad_control)                      \
     FEATURE(KHR, WorkgroupMemoryExplicitLayout, WORKGROUP_MEMORY_EXPLICIT_LAYOUT,                  \
             workgroup_memory_explicit_layout)
 
@@ -483,6 +484,11 @@ FN_MAX_LIMIT_LIST
         return extensions.workgroup_memory_explicit_layout;
     }
 
+    /// Returns true if the device supports VK_KHR_shader_quad_control.
+    bool IsKhrShaderQuadControlSupported() const {
+        return extensions.shader_quad_control && features.shader_quad_control.shaderQuadControl;
+    }
+
     /// Returns true if the device supports VK_KHR_image_format_list.
     bool IsKhrImageFormatListSupported() const {
         return extensions.image_format_list || instance_version >= VK_API_VERSION_1_2;