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@ -17,6 +17,7 @@ using Tegra::Shader::ShuffleOperation; |
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using Tegra::Shader::VoteOperation; |
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using Tegra::Shader::VoteOperation; |
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namespace { |
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namespace { |
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OperationCode GetOperationCode(VoteOperation vote_op) { |
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OperationCode GetOperationCode(VoteOperation vote_op) { |
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switch (vote_op) { |
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switch (vote_op) { |
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case VoteOperation::All: |
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case VoteOperation::All: |
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@ -30,6 +31,7 @@ OperationCode GetOperationCode(VoteOperation vote_op) { |
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return OperationCode::VoteAll; |
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return OperationCode::VoteAll; |
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} |
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} |
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} |
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} |
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} // Anonymous namespace
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} // Anonymous namespace
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u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) { |
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u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) { |
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@ -46,50 +48,50 @@ u32 ShaderIR::DecodeWarp(NodeBlock& bb, u32 pc) { |
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break; |
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break; |
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} |
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} |
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case OpCode::Id::SHFL: { |
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case OpCode::Id::SHFL: { |
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Node width = [this, instr] { |
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm)) |
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Node mask = instr.shfl.is_mask_imm ? Immediate(static_cast<u32>(instr.shfl.mask_imm)) |
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: GetRegister(instr.gpr39); |
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: GetRegister(instr.gpr39); |
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Node index = instr.shfl.is_index_imm ? Immediate(static_cast<u32>(instr.shfl.index_imm)) |
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: GetRegister(instr.gpr20); |
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// Convert the obscure SHFL mask back into GL_NV_shader_thread_shuffle's width. This has
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// been done reversing Nvidia's math. It won't work on all cases due to SHFL having
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// different parameters that don't properly map to GLSL's interface, but it should work
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// for cases emitted by Nvidia's compiler.
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if (instr.shfl.operation == ShuffleOperation::Up) { |
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return Operation( |
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OperationCode::ILogicalShiftRight, |
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Operation(OperationCode::IAdd, std::move(mask), Immediate(-0x2000)), |
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Immediate(8)); |
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} else { |
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return Operation(OperationCode::ILogicalShiftRight, |
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Operation(OperationCode::IAdd, Immediate(0x201F), |
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Operation(OperationCode::INegate, std::move(mask))), |
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Immediate(8)); |
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} |
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}(); |
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Node thread_id = Operation(OperationCode::ThreadId); |
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Node clamp = Operation(OperationCode::IBitwiseAnd, mask, Immediate(0x1FU)); |
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Node seg_mask = BitfieldExtract(mask, 8, 16); |
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Node neg_seg_mask = Operation(OperationCode::IBitwiseNot, seg_mask); |
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Node min_thread_id = Operation(OperationCode::IBitwiseAnd, thread_id, seg_mask); |
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Node max_thread_id = Operation(OperationCode::IBitwiseOr, min_thread_id, |
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Operation(OperationCode::IBitwiseAnd, clamp, neg_seg_mask)); |
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const auto [operation, in_range] = [instr]() -> std::pair<OperationCode, OperationCode> { |
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Node src_thread_id = [instr, index, neg_seg_mask, min_thread_id, thread_id] { |
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switch (instr.shfl.operation) { |
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switch (instr.shfl.operation) { |
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case ShuffleOperation::Idx: |
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case ShuffleOperation::Idx: |
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return {OperationCode::ShuffleIndexed, OperationCode::InRangeShuffleIndexed}; |
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case ShuffleOperation::Up: |
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return {OperationCode::ShuffleUp, OperationCode::InRangeShuffleUp}; |
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return Operation(OperationCode::IBitwiseOr, |
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Operation(OperationCode::IBitwiseAnd, index, neg_seg_mask), |
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min_thread_id); |
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case ShuffleOperation::Down: |
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case ShuffleOperation::Down: |
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return {OperationCode::ShuffleDown, OperationCode::InRangeShuffleDown}; |
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return Operation(OperationCode::IAdd, thread_id, index); |
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case ShuffleOperation::Up: |
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return Operation(OperationCode::IAdd, thread_id, |
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Operation(OperationCode::INegate, index)); |
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case ShuffleOperation::Bfly: |
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case ShuffleOperation::Bfly: |
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return {OperationCode::ShuffleButterfly, OperationCode::InRangeShuffleButterfly}; |
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return Operation(OperationCode::IBitwiseXor, thread_id, index); |
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} |
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} |
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UNREACHABLE_MSG("Invalid SHFL operation: {}", |
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static_cast<u64>(instr.shfl.operation.Value())); |
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return {}; |
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UNREACHABLE(); |
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return Immediate(0U); |
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}(); |
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}(); |
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// Setting the predicate before the register is intentional to avoid overwriting.
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Node index = instr.shfl.is_index_imm ? Immediate(static_cast<u32>(instr.shfl.index_imm)) |
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: GetRegister(instr.gpr20); |
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SetPredicate(bb, instr.shfl.pred48, Operation(in_range, index, width)); |
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Node in_bounds = [instr, src_thread_id, min_thread_id, max_thread_id] { |
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if (instr.shfl.operation == ShuffleOperation::Up) { |
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return Operation(OperationCode::LogicalIGreaterEqual, src_thread_id, min_thread_id); |
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} else { |
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return Operation(OperationCode::LogicalILessEqual, src_thread_id, max_thread_id); |
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} |
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}(); |
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SetPredicate(bb, instr.shfl.pred48, in_bounds); |
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SetRegister( |
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SetRegister( |
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bb, instr.gpr0, |
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bb, instr.gpr0, |
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Operation(operation, GetRegister(instr.gpr8), std::move(index), std::move(width))); |
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Operation(OperationCode::ShuffleIndexed, GetRegister(instr.gpr8), src_thread_id)); |
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break; |
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break; |
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} |
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} |
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default: |
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default: |
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