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@ -985,8 +985,10 @@ void RasterizerVulkan::UpdateDynamicStates() { |
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if (regs.logic_op.enable) { |
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if (regs.logic_op.enable) { |
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regs.logic_op.enable = static_cast<u32>(!has_float); |
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regs.logic_op.enable = static_cast<u32>(!has_float); |
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} |
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} |
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} |
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UpdateLogicOpEnable(regs); |
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UpdateLogicOpEnable(regs); |
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} else { |
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UpdateLogicOpEnable(regs); |
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} |
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UpdateDepthClampEnable(regs); |
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UpdateDepthClampEnable(regs); |
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UpdateLineStippleEnable(regs); |
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UpdateLineStippleEnable(regs); |
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UpdateConservativeRasterizationMode(regs); |
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UpdateConservativeRasterizationMode(regs); |
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@ -1614,7 +1616,7 @@ void RasterizerVulkan::UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs) |
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highest_dirty_attr = index; |
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highest_dirty_attr = index; |
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} |
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} |
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} |
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} |
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for (size_t index = 0; index < highest_dirty_attr; ++index) { |
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for (size_t index = 0; index <= highest_dirty_attr; ++index) { |
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const Maxwell::VertexAttribute attribute{regs.vertex_attrib_format[index]}; |
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const Maxwell::VertexAttribute attribute{regs.vertex_attrib_format[index]}; |
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const u32 binding{attribute.buffer}; |
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const u32 binding{attribute.buffer}; |
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dirty[Dirty::VertexAttribute0 + index] = false; |
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dirty[Dirty::VertexAttribute0 + index] = false; |
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