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@ -4696,18 +4696,15 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { |
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { |
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if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { |
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mrc_inst* inst_cream = (mrc_inst*)inst_base->component; |
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mrc_inst* inst_cream = (mrc_inst*)inst_base->component; |
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unsigned int inst = inst_cream->inst; |
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if (inst_cream->cp_num == 15) { |
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const uint32_t value = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2); |
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if (inst_cream->Rd == 15) { |
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if (inst_cream->Rd == 15) { |
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DEBUG_MSG; |
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} |
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if (inst_cream->inst == 0xeef04a10) { |
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// Undefined instruction fmrx
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RD = 0x20000000; |
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CITRA_IGNORE_EXIT(-1); |
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goto END; |
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cpu->Cpsr = (cpu->Cpsr & ~0xF0000000) | (value & 0xF0000000); |
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LOAD_NZCVT; |
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} else { |
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} else { |
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if (inst_cream->cp_num == 15) |
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RD = cpu->ReadCP15Register(CRn, OPCODE_1, CRm, OPCODE_2); |
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RD = value; |
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} |
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} |
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} |
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} |
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} |
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cpu->Reg[15] += cpu->GetInstructionSize(); |
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cpu->Reg[15] += cpu->GetInstructionSize(); |
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