fix nce cache invalidation and signal interrupt

- ClearInstructionCache: use IC IALLU instead of just memory barriers
- InvalidateCacheRange: actually implement per-cache-line invalidation
- SignalInterrupt: add memory fence for is_running visibility

src/core/arm/nce/arm_nce.cpp

@@ -371,10 +371,12 @@ void ArmNce::SignalInterrupt(Kernel::KThread* thread) {
     // Add break loop condition.
     m_guest_ctx.esr_el1.fetch_or(static_cast<u64>(HaltReason::BreakLoop));
 
-    // Lock the thread context.
     auto* params = &thread->GetNativeExecutionParameters();
     LockThreadParameters(params);
 
+    // Ensure visibility of is_running after lock acquire
+    std::atomic_thread_fence(std::memory_order_acquire);
+
     if (params->is_running) {
         // We should signal to the running thread.
         // The running thread will unlock the thread context.
@@ -389,15 +391,28 @@ const std::size_t CACHE_PAGE_SIZE = 4096;
 
 void ArmNce::ClearInstructionCache() {
 #ifdef __aarch64__
-    // Ensure all previous memory operations complete
-    asm volatile("dmb ish" ::: "memory");
-    asm volatile("dsb ish" ::: "memory");
-    asm volatile("isb" ::: "memory");
+    // Use IC IALLU to actually invalidate L1 instruction cache
+    asm volatile("dsb ish\n"
+                 "ic iallu\n"
+                 "dsb ish\n"
+                 "isb" ::: "memory");
 #endif
 }
 
 void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) {
-    this->ClearInstructionCache();
+#ifdef __aarch64__
+    // Invalidate instruction cache for specific range instead of full flush
+    constexpr u64 cache_line_size = 64;
+    const u64 aligned_addr = addr & ~(cache_line_size - 1);
+    const u64 end_addr = (addr + size + cache_line_size - 1) & ~(cache_line_size - 1);
+
+    asm volatile("dsb ish" ::: "memory");
+    for (u64 i = aligned_addr; i < end_addr; i += cache_line_size) {
+        asm volatile("ic ivau, %0" :: "r"(i) : "memory");
+    }
+    asm volatile("dsb ish\n"
+                 "isb" ::: "memory");
+#endif
 }
 
 } // namespace Core