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@ -4964,6 +4964,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { |
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} |
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} |
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MSR_INST: |
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MSR_INST: |
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{ |
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{ |
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if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { |
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msr_inst *inst_cream = (msr_inst *)inst_base->component; |
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msr_inst *inst_cream = (msr_inst *)inst_base->component; |
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const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; |
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const uint32_t UnallocMask = 0x06f0fc00, UserMask = 0xf80f0200, PrivMask = 0x000001df, StateMask = 0x01000020; |
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unsigned int inst = inst_cream->inst; |
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unsigned int inst = inst_cream->inst; |
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@ -4999,6 +5000,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) { |
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cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); |
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cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); |
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} |
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} |
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} |
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} |
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} |
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cpu->Reg[15] += GET_INST_SIZE(cpu); |
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cpu->Reg[15] += GET_INST_SIZE(cpu); |
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INC_PC(sizeof(msr_inst)); |
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INC_PC(sizeof(msr_inst)); |
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FETCH_INST; |
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FETCH_INST; |
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