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@ -52,12 +52,15 @@ void DrawManager::ProcessMethodCall(u32 method, u32 argument) { |
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} |
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void DrawManager::Clear(u32 layer_count) { |
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maxwell3d->rasterizer->Clear(layer_count); |
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if (maxwell3d->ShouldExecute()) { |
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maxwell3d->rasterizer->Clear(layer_count); |
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} |
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} |
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void DrawManager::DrawDeferred() { |
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if (draw_state.draw_mode != DrawMode::Instance || draw_state.instance_count == 0) |
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if (draw_state.draw_mode != DrawMode::Instance || draw_state.instance_count == 0) { |
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return; |
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} |
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DrawEnd(draw_state.instance_count + 1, true); |
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draw_state.instance_count = 0; |
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} |
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@ -112,8 +115,9 @@ void DrawManager::DrawEnd(u32 instance_count, bool force_draw) { |
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const auto& regs{maxwell3d->regs}; |
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switch (draw_state.draw_mode) { |
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case DrawMode::Instance: |
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if (!force_draw) |
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if (!force_draw) { |
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break; |
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} |
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[[fallthrough]]; |
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case DrawMode::General: |
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draw_state.base_instance = regs.global_base_instance_index; |
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@ -185,7 +189,8 @@ void DrawManager::ProcessDraw(bool draw_indexed, u32 instance_count) { |
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UpdateTopology(); |
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if (maxwell3d->ShouldExecute()) |
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if (maxwell3d->ShouldExecute()) { |
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maxwell3d->rasterizer->Draw(draw_indexed, instance_count); |
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} |
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} |
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} // namespace Tegra::Engines
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