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@ -32,21 +32,21 @@ enum class Shift : u64 { |
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IR::U32 scaleIndex(IR::IREmitter& ir, IR::U32 index, Shift shift) { |
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switch (shift) { |
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case Shift::Default: return index; |
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case Shift::U16: return ir.ShiftLeftLogical(index, ir.Imm32(1)); |
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case Shift::B32: return ir.ShiftLeftLogical(index, ir.Imm32(2)); |
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default: UNREACHABLE(); |
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case Shift::Default: return index; |
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case Shift::U16: return ir.ShiftLeftLogical(index, ir.Imm32(1)); |
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case Shift::B32: return ir.ShiftLeftLogical(index, ir.Imm32(2)); |
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default: UNREACHABLE(); |
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} |
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} |
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IR::U32 skewBytes(IR::IREmitter& ir, SZ sizeRead) { |
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const IR::U32 lane = ir.LaneId(); |
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switch (sizeRead) { |
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case SZ::U8: return lane; |
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case SZ::U16: return ir.ShiftLeftLogical(lane, ir.Imm32(1)); |
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case SZ::U32: |
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case SZ::F32: return ir.ShiftLeftLogical(lane, ir.Imm32(2)); |
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default: UNREACHABLE(); |
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case SZ::U8: return lane; |
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case SZ::U16: return ir.ShiftLeftLogical(lane, ir.Imm32(1)); |
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case SZ::U32: |
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case SZ::F32: return ir.ShiftLeftLogical(lane, ir.Imm32(2)); |
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default: UNREACHABLE(); |
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} |
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} |
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@ -88,7 +88,7 @@ void TranslatorVisitor::ISBERD(u64 insn) { |
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case SZ::U16: globalLoaded = ir.LoadGlobalU16(index64); break; |
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case SZ::U32: |
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case SZ::F32: globalLoaded = ir.LoadGlobal32(index64); break; |
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default: UNREACHABLE(); |
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default: UNREACHABLE(); |
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} |
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X(isberd.dest_reg.Value(), globalLoaded); |
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@ -102,10 +102,13 @@ void TranslatorVisitor::ISBERD(u64 insn) { |
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IR::F32 float_index{}; |
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switch (isberd.mode.Value()) { |
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case Mode::Patch: float_index = ir.GetPatch(index.Patch()); break; |
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case Mode::Prim: float_index = ir.GetAttribute(index.Attribute()); break; |
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case Mode::Attr: float_index = ir.GetAttributeIndexed(index); break; |
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default: UNREACHABLE(); |
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case Mode::Patch: float_index = ir.GetPatch(index.Patch()); |
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break; |
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case Mode::Prim: float_index = ir.GetAttribute(index.Attribute()); |
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break; |
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case Mode::Attr: float_index = ir.GetAttributeIndexed(index); |
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break; |
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default: UNREACHABLE(); |
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} |
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X(isberd.dest_reg.Value(), ir.BitCast<IR::U32>(float_index)); |
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