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@ -18,6 +18,32 @@ u32 ShaderIR::DecodeConversion(BasicBlock& bb, u32 pc) { |
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const auto opcode = OpCode::Decode(instr); |
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switch (opcode->get().GetId()) { |
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case OpCode::Id::I2I_R: { |
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UNIMPLEMENTED_IF(instr.conversion.selector); |
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const bool input_signed = instr.conversion.is_input_signed; |
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const bool output_signed = instr.conversion.is_output_signed; |
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Node value = GetRegister(instr.gpr20); |
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value = ConvertIntegerSize(value, instr.conversion.src_size, input_signed); |
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value = GetOperandAbsNegInteger(value, instr.conversion.abs_a, instr.conversion.negate_a, |
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input_signed); |
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if (input_signed != output_signed) { |
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value = SignedOperation(OperationCode::ICastUnsigned, output_signed, NO_PRECISE, value); |
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} |
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SetRegister(bb, instr.gpr0, value); |
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if (instr.generates_cc) { |
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const Node zero_condition = |
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SignedOperation(OperationCode::LogicalIEqual, output_signed, value, Immediate(0)); |
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SetInternalFlag(bb, InternalFlag::Zero, zero_condition); |
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LOG_WARNING(HW_GPU, "I2I Condition codes implementation is incomplete."); |
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} |
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break; |
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} |
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case OpCode::Id::I2F_R: |
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case OpCode::Id::I2F_C: { |
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UNIMPLEMENTED_IF(instr.conversion.dest_size != Register::Size::Word); |
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