eden-emu/eden - eden - InfoTonic

MerryMage 5559dc7a61 externals: Update dynarmic to 73d3efc 73d3efc emit_x64_floating_point: Deduplicate code c9508c3 fuzz_with_unicorn: Randomize FPCR.DN 2970833 emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1 150764f emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1 b7d209c IR: SSE4.1 implementation of FPVectorRoundInt 8cf8270 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant 8f46c26 IR: Initial implementation of FPVectorRoundInt 97017bb A64: Implement SQADD and SQSUB, scalar variant ce58863 IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths e80f8ff a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument 1e4ec7e simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function 6f9dc9b A64: Implement SMAXP, SMINP, UMAXP, UMINP 1dfb29f ir: Add opcodes for vector paired maximum and minimums 017b510 A64: Implement SMAXV, SMINV, UMAXV, and UMINV aae22ee ir: Add opcodes for performing scalar integral min/max 6ef3af3 A64: Implement PMULL{2} 2a4ce19 translate: Deduplicate GetDataSize() functions 0e01500 floating_point_{conditional}_compare: Deduplicate code 259237c common: Move all cryptographic function to common/crypto c5f1080 a32_emit_x64: BMI2 implementation of A32SetCpsr a23304a a32_emit_x64: Shorten EmitA32GetCpsr 57604d2 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid 945fa48 A64: Implement PMUL 656a404 ir: Add opcode for performing polynomial multiplication 05143df A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant 34ce767 A64: Implement FCVTZS (vector, integer), single/double variant 0f9bc2d IR: Implement FPVectorTo{Signed,Unsigned}Fixed 0189e44 fp/info: Replace constant value generators with FPValue db16568 emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min} 31148bd emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs 4c3ca51 A64: Implement FMAX's vector single and double precision variants bf0f21c A64: Implement FMIN's vector single and double precision variants 76f0ca0 IR: Implement FPVector{Max,Min} 6c37c31 FPRecipEstimate: Move offset out of function 59546f3 microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits 3f6b03a A64: Implement FRECPS, vector/scalar single/double variants 2d2ca5e IR: Implement FPRecipStepFused, FPVectorRecipStepFused 5cb9f1d A64: Implement FRECPE, vector single/double variant c5a14ab IR: Implement FPVectorRecipEstimate 56f8a0b A64: Implement FRECPE, scalar single/double variant fde69b4 IR: Implement FPRecipEstimate 186e52c IR: Implement FPRecipEstimate cf2e1ae fp: Change FPUnpacked to a normalized representation	8 years ago
..
pre-commit	pre-commit: Change comment from citra to yuzu	8 years ago

MerryMage 5559dc7a61 externals: Update dynarmic to 73d3efc

73d3efc emit_x64_floating_point: Deduplicate code
c9508c3 fuzz_with_unicorn: Randomize FPCR.DN
2970833 emit_x64_vector_floating_point: Fix FPVector{Max,Min} when FPCR.DN = 1
150764f emit_x64_floating_point: Fix FP{Max,Min} when FPCR.DN = 1
b7d209c IR: SSE4.1 implementation of FPVectorRoundInt
8cf8270 A64: Implement FRINT{N,M,P,Z,A,X,I} (vector), single/double variant
8f46c26 IR: Initial implementation of FPVectorRoundInt
97017bb A64: Implement SQADD and SQSUB, scalar variant
ce58863 IR: Generalise SignedSaturated{Add,Sub} to support more bitwidths
e80f8ff a64_emit_x64: Bugfix EmitA64OrQC - Incorrect argument
1e4ec7e simd_three_same: Extract non-paired SMAX, SMIN, UMAX, UMIN code to a common function
6f9dc9b A64: Implement SMAXP, SMINP, UMAXP, UMINP
1dfb29f ir: Add opcodes for vector paired maximum and minimums
017b510 A64: Implement SMAXV, SMINV, UMAXV, and UMINV
aae22ee ir: Add opcodes for performing scalar integral min/max
6ef3af3 A64: Implement PMULL{2}
2a4ce19 translate: Deduplicate GetDataSize() functions
0e01500 floating_point_{conditional}_compare: Deduplicate code
259237c common: Move all cryptographic function to common/crypto
c5f1080 a32_emit_x64: BMI2 implementation of A32SetCpsr
a23304a a32_emit_x64: Shorten EmitA32GetCpsr
57604d2 a32_emit_x64: Assert that memory layout assumption in EmitA32GetCpsr is valid
945fa48 A64: Implement PMUL
656a404 ir: Add opcode for performing polynomial multiplication
05143df A64: Implement FCVT{N,M,A,P}{U,S} (vector), FCVTZU (vector, integer), single/double variant
34ce767 A64: Implement FCVTZS (vector, integer), single/double variant
0f9bc2d IR: Implement FPVectorTo{Signed,Unsigned}Fixed
0189e44 fp/info: Replace constant value generators with FPValue
db16568 emit_x64_vector_floating_point: AVX implementation of FPVector{Max,Min}
31148bd emit_x64_vector_floating_point: Remove unnecessary double jump in HandleNaNs
4c3ca51 A64: Implement FMAX's vector single and double precision variants
bf0f21c A64: Implement FMIN's vector single and double precision variants
76f0ca0 IR: Implement FPVector{Max,Min}
6c37c31 FPRecipEstimate: Move offset out of function
59546f3 microinstruction: Update ReadsFromAndWritesToFPSRCumulativeExceptionBits
3f6b03a A64: Implement FRECPS, vector/scalar single/double variants
2d2ca5e IR: Implement FPRecipStepFused, FPVectorRecipStepFused
5cb9f1d A64: Implement FRECPE, vector single/double variant
c5a14ab IR: Implement FPVectorRecipEstimate
56f8a0b A64: Implement FRECPE, scalar single/double variant
fde69b4 IR: Implement FPRecipEstimate
186e52c IR: Implement FPRecipEstimate
cf2e1ae fp: Change FPUnpacked to a normalized representation

8 years ago

pre-commit

pre-commit: Change comment from citra to yuzu

8 years ago