Update src/shader_recompiler/frontend/maxwell/translate/impl/surface_atomic_operations.cpp

src/shader_recompiler/frontend/maxwell/translate/impl/surface_atomic_operations.cpp

@@ -198,17 +198,19 @@ void TranslatorVisitor::SURED(u64 insn) {
     // SURED unlike SUATOM does NOT have a binded register
     union {
         u64 raw;
-        BitField<24, 3, AtomicOp> op; //OK - 24 (SURedOp)
-        BitField<33, 3, Type> type; //OK? - 33 (Dim)
-        BitField<20, 3, Size> size; //?
-        BitField<49, 2, Clamp> clamp; //OK - 49 (Clamp4)
-        BitField<0, 8, IR::Reg> operand_reg; //RA?
-        BitField<8, 8, IR::Reg> coord_reg; //RB?
-        BitField<36, 13, u64> bound_offset; //OK 33 (TidB)
+        BitField<51, 1, u64> is_bound;
+        BitField<21, 3, AtomicOp> op;
+        BitField<33, 3, Type> type;
+        BitField<20, 3, Size> size;
+        BitField<49, 2, Clamp> clamp;
+        BitField<0, 8, IR::Reg> operand_reg;
+        BitField<8, 8, IR::Reg> coord_reg;
+        BitField<36, 13, u64> bound_offset;    // is_bound
+        BitField<39, 8, IR::Reg> bindless_reg; // !is_bound
     } const sured{insn};
     ImageAtomOp(*this, IR::Reg::RZ, sured.operand_reg, sured.coord_reg, sured.bindless_reg,
                 sured.op, sured.clamp, sured.size, sured.type, sured.bound_offset,
                 sured.is_bound == 0, false);
 }
 
-} // namespace Shader::Maxwell
+} // namespace Shader::Maxwell