Liam
2 years ago
9 changed files with 3850 additions and 44 deletions
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3src/android/app/build.gradle.kts
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8src/core/CMakeLists.txt
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102src/core/arm/nce/arm_nce.cpp
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13src/core/arm/nce/arm_nce.h
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60src/core/arm/nce/arm_nce.s
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3src/core/arm/nce/arm_nce_asm_definitions.h
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825src/core/arm/nce/interpreter_visitor.cpp
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103src/core/arm/nce/interpreter_visitor.h
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2777src/core/arm/nce/visitor_base.h
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// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs>
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/bit_cast.h"
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#include "core/arm/nce/interpreter_visitor.h"
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#include <dynarmic/frontend/A64/decoder/a64.h>
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namespace Core { |
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template <u32 BitSize> |
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u64 SignExtendToLong(u64 value) { |
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u64 mask = 1ULL << (BitSize - 1); |
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value &= (1ULL << BitSize) - 1; |
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return (value ^ mask) - mask; |
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} |
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static u64 SignExtendToLong(u64 value, u64 bitsize) { |
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switch (bitsize) { |
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case 8: |
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return SignExtendToLong<8>(value); |
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case 16: |
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return SignExtendToLong<16>(value); |
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case 32: |
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return SignExtendToLong<32>(value); |
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default: |
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return value; |
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} |
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} |
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template <u64 BitSize> |
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u32 SignExtendToWord(u32 value) { |
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u32 mask = 1ULL << (BitSize - 1); |
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value &= (1ULL << BitSize) - 1; |
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return (value ^ mask) - mask; |
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} |
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static u32 SignExtendToWord(u32 value, u64 bitsize) { |
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switch (bitsize) { |
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case 8: |
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return SignExtendToWord<8>(value); |
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case 16: |
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return SignExtendToWord<16>(value); |
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default: |
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return value; |
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} |
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} |
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static u64 SignExtend(u64 value, u64 bitsize, u64 regsize) { |
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if (regsize == 64) { |
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return SignExtendToLong(value, bitsize); |
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} else { |
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return SignExtendToWord(static_cast<u32>(value), bitsize); |
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} |
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} |
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static u128 VectorGetElement(u128 value, u64 bitsize) { |
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switch (bitsize) { |
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case 8: |
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return {value[0] & ((1ULL << 8) - 1), 0}; |
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case 16: |
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return {value[0] & ((1ULL << 16) - 1), 0}; |
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case 32: |
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return {value[0] & ((1ULL << 32) - 1), 0}; |
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case 64: |
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return {value[0], 0}; |
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default: |
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return value; |
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} |
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} |
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u64 InterpreterVisitor::ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift) { |
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ASSERT(shift <= 4); |
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ASSERT(bitsize == 32 || bitsize == 64); |
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u64 val = this->GetReg(reg); |
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size_t len; |
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u64 extended; |
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bool signed_extend; |
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switch (option.ZeroExtend()) { |
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case 0b000: { // UXTB
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val &= ((1ULL << 8) - 1); |
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len = 8; |
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signed_extend = false; |
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break; |
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} |
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case 0b001: { // UXTH
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val &= ((1ULL << 16) - 1); |
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len = 16; |
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signed_extend = false; |
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break; |
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} |
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case 0b010: { // UXTW
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val &= ((1ULL << 32) - 1); |
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len = 32; |
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signed_extend = false; |
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break; |
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} |
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case 0b011: { // UXTX
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len = 64; |
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signed_extend = false; |
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break; |
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} |
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case 0b100: { // SXTB
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val &= ((1ULL << 8) - 1); |
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len = 8; |
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signed_extend = true; |
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break; |
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} |
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case 0b101: { // SXTH
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val &= ((1ULL << 16) - 1); |
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len = 16; |
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signed_extend = true; |
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break; |
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} |
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case 0b110: { // SXTW
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val &= ((1ULL << 32) - 1); |
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len = 32; |
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signed_extend = true; |
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break; |
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} |
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case 0b111: { // SXTX
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len = 64; |
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signed_extend = true; |
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break; |
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} |
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default: |
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UNREACHABLE(); |
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} |
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if (len < bitsize && signed_extend) { |
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extended = SignExtend(val, len, bitsize); |
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} else { |
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extended = val; |
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} |
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return extended << shift; |
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} |
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u128 InterpreterVisitor::GetVec(Vec v) { |
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return m_fpsimd_regs[static_cast<u32>(v)]; |
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} |
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u64 InterpreterVisitor::GetReg(Reg r) { |
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return m_regs[static_cast<u32>(r)]; |
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} |
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u64 InterpreterVisitor::GetSp() { |
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return m_sp; |
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} |
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u64 InterpreterVisitor::GetPc() { |
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return m_pc; |
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} |
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void InterpreterVisitor::SetVec(Vec v, u128 value) { |
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m_fpsimd_regs[static_cast<u32>(v)] = value; |
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} |
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void InterpreterVisitor::SetReg(Reg r, u64 value) { |
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m_regs[static_cast<u32>(r)] = value; |
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} |
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void InterpreterVisitor::SetSp(u64 value) { |
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m_sp = value; |
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} |
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bool InterpreterVisitor::Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt) { |
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const auto memop = L ? MemOp::Load : MemOp::Store; |
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const size_t elsize = 8 << size; |
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const size_t datasize = elsize; |
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// Operation
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const size_t dbytes = datasize / 8; |
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u64 address; |
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if (Rn == Reg::SP) { |
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address = this->GetSp(); |
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} else { |
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address = this->GetReg(Rn); |
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} |
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switch (memop) { |
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case MemOp::Store: { |
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std::atomic_thread_fence(std::memory_order_seq_cst); |
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u64 value = this->GetReg(Rt); |
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m_memory.WriteBlock(address, &value, dbytes); |
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std::atomic_thread_fence(std::memory_order_seq_cst); |
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break; |
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} |
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case MemOp::Load: { |
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u64 value = 0; |
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m_memory.ReadBlock(address, &value, dbytes); |
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this->SetReg(Rt, value); |
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std::atomic_thread_fence(std::memory_order_seq_cst); |
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break; |
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} |
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default: |
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UNREACHABLE(); |
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} |
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return true; |
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} |
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bool InterpreterVisitor::STLLR(Imm<2> sz, Reg Rn, Reg Rt) { |
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const size_t size = sz.ZeroExtend<size_t>(); |
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const bool L = 0; |
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const bool o0 = 0; |
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return this->Ordered(size, L, o0, Rn, Rt); |
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} |
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bool InterpreterVisitor::STLR(Imm<2> sz, Reg Rn, Reg Rt) { |
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const size_t size = sz.ZeroExtend<size_t>(); |
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const bool L = 0; |
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const bool o0 = 1; |
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return this->Ordered(size, L, o0, Rn, Rt); |
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} |
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bool InterpreterVisitor::LDLAR(Imm<2> sz, Reg Rn, Reg Rt) { |
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const size_t size = sz.ZeroExtend<size_t>(); |
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const bool L = 1; |
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const bool o0 = 0; |
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return this->Ordered(size, L, o0, Rn, Rt); |
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} |
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bool InterpreterVisitor::LDAR(Imm<2> sz, Reg Rn, Reg Rt) { |
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const size_t size = sz.ZeroExtend<size_t>(); |
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const bool L = 1; |
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const bool o0 = 1; |
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return this->Ordered(size, L, o0, Rn, Rt); |
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} |
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bool InterpreterVisitor::LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) { |
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const size_t size = opc_0 == 0 ? 4 : 8; |
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const s64 offset = Dynarmic::concatenate(imm19, Imm<2>{0}).SignExtend<s64>(); |
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const u64 address = this->GetPc() + offset; |
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u64 data = 0; |
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m_memory.ReadBlock(address, &data, size); |
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this->SetReg(Rt, data); |
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return true; |
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} |
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bool InterpreterVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) { |
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if (opc == 0b11) { |
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// Unallocated encoding
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return false; |
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} |
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const u64 size = 4 << opc.ZeroExtend(); |
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const u64 offset = imm19.SignExtend<u64>() << 2; |
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const u64 address = this->GetPc() + offset; |
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u128 data{}; |
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m_memory.ReadBlock(address, &data, size); |
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this->SetVec(Vt, data); |
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return true; |
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} |
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bool InterpreterVisitor::STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, |
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Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) { |
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if ((L == 0 && opc.Bit<0>() == 1) || opc == 0b11) { |
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// Unallocated encoding
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return false; |
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} |
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const auto memop = L == 1 ? MemOp::Load : MemOp::Store; |
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if (memop == MemOp::Load && wback && (Rt == Rn || Rt2 == Rn) && Rn != Reg::R31) { |
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// Unpredictable instruction
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return false; |
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} |
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if (memop == MemOp::Store && wback && (Rt == Rn || Rt2 == Rn) && Rn != Reg::R31) { |
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// Unpredictable instruction
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return false; |
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} |
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if (memop == MemOp::Load && Rt == Rt2) { |
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// Unpredictable instruction
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return false; |
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} |
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u64 address; |
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if (Rn == Reg::SP) { |
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address = this->GetSp(); |
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} else { |
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address = this->GetReg(Rn); |
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} |
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const bool postindex = !not_postindex; |
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const bool signed_ = opc.Bit<0>() != 0; |
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const size_t scale = 2 + opc.Bit<1>(); |
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const size_t datasize = 8 << scale; |
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const u64 offset = imm7.SignExtend<u64>() << scale; |
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if (!postindex) { |
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address += offset; |
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} |
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const size_t dbytes = datasize / 8; |
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switch (memop) { |
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case MemOp::Store: { |
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u64 data1 = this->GetReg(Rt); |
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u64 data2 = this->GetReg(Rt2); |
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m_memory.WriteBlock(address, &data1, dbytes); |
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m_memory.WriteBlock(address + dbytes, &data2, dbytes); |
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break; |
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} |
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case MemOp::Load: { |
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u64 data1 = 0, data2 = 0; |
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m_memory.ReadBlock(address, &data1, dbytes); |
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m_memory.ReadBlock(address + dbytes, &data2, dbytes); |
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if (signed_) { |
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this->SetReg(Rt, SignExtend(data1, datasize, 64)); |
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this->SetReg(Rt2, SignExtend(data2, datasize, 64)); |
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} else { |
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this->SetReg(Rt, data1); |
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this->SetReg(Rt2, data2); |
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} |
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break; |
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} |
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default: |
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UNREACHABLE(); |
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} |
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if (wback) { |
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if (postindex) { |
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address += offset; |
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} |
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if (Rn == Reg::SP) { |
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this->SetSp(address); |
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} else { |
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this->SetReg(Rn, address); |
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} |
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} |
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return true; |
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} |
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bool InterpreterVisitor::STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, |
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Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) { |
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if (opc == 0b11) { |
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// Unallocated encoding
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return false; |
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} |
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const auto memop = L == 1 ? MemOp::Load : MemOp::Store; |
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if (memop == MemOp::Load && Vt == Vt2) { |
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// Unpredictable instruction
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return false; |
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} |
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u64 address; |
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if (Rn == Reg::SP) { |
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address = this->GetSp(); |
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} else { |
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address = this->GetReg(Rn); |
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} |
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const bool postindex = !not_postindex; |
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const size_t scale = 2 + opc.ZeroExtend<size_t>(); |
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const size_t datasize = 8 << scale; |
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const u64 offset = imm7.SignExtend<u64>() << scale; |
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const size_t dbytes = datasize / 8; |
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if (!postindex) { |
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address += offset; |
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} |
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switch (memop) { |
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case MemOp::Store: { |
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u128 data1 = VectorGetElement(this->GetVec(Vt), datasize); |
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u128 data2 = VectorGetElement(this->GetVec(Vt2), datasize); |
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m_memory.WriteBlock(address, &data1, dbytes); |
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m_memory.WriteBlock(address + dbytes, &data2, dbytes); |
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break; |
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} |
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case MemOp::Load: { |
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u128 data1{}, data2{}; |
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m_memory.ReadBlock(address, &data1, dbytes); |
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m_memory.ReadBlock(address + dbytes, &data2, dbytes); |
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this->SetVec(Vt, data1); |
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this->SetVec(Vt2, data2); |
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break; |
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} |
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default: |
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UNREACHABLE(); |
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} |
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if (wback) { |
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if (postindex) { |
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address += offset; |
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} |
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if (Rn == Reg::SP) { |
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this->SetSp(address); |
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} else { |
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this->SetReg(Rn, address); |
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} |
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} |
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return true; |
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} |
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bool InterpreterVisitor::RegisterImmediate(bool wback, bool postindex, size_t scale, u64 offset, |
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Imm<2> size, Imm<2> opc, Reg Rn, Reg Rt) { |
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MemOp memop; |
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bool signed_ = false; |
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size_t regsize = 0; |
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if (opc.Bit<1>() == 0) { |
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memop = opc.Bit<0>() ? MemOp::Load : MemOp::Store; |
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regsize = size == 0b11 ? 64 : 32; |
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signed_ = false; |
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} else if (size == 0b11) { |
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memop = MemOp::Prefetch; |
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ASSERT(!opc.Bit<0>()); |
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} else { |
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memop = MemOp::Load; |
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ASSERT(!(size == 0b10 && opc.Bit<0>() == 1)); |
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regsize = opc.Bit<0>() ? 32 : 64; |
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signed_ = true; |
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} |
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if (memop == MemOp::Load && wback && Rn == Rt && Rn != Reg::R31) { |
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// Unpredictable instruction
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return false; |
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} |
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if (memop == MemOp::Store && wback && Rn == Rt && Rn != Reg::R31) { |
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// Unpredictable instruction
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return false; |
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} |
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u64 address; |
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if (Rn == Reg::SP) { |
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address = this->GetSp(); |
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} else { |
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address = this->GetReg(Rn); |
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} |
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if (!postindex) { |
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address += offset; |
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} |
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const size_t datasize = 8 << scale; |
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switch (memop) { |
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case MemOp::Store: { |
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u64 data = this->GetReg(Rt); |
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m_memory.WriteBlock(address, &data, datasize / 8); |
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break; |
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} |
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case MemOp::Load: { |
||||
|
u64 data = 0; |
||||
|
m_memory.ReadBlock(address, &data, datasize / 8); |
||||
|
if (signed_) { |
||||
|
this->SetReg(Rt, SignExtend(data, datasize, regsize)); |
||||
|
} else { |
||||
|
this->SetReg(Rt, data); |
||||
|
} |
||||
|
break; |
||||
|
} |
||||
|
case MemOp::Prefetch: |
||||
|
// this->Prefetch(address, Rt)
|
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
if (wback) { |
||||
|
if (postindex) { |
||||
|
address += offset; |
||||
|
} |
||||
|
|
||||
|
if (Rn == Reg::SP) { |
||||
|
this->SetSp(address); |
||||
|
} else { |
||||
|
this->SetReg(Rn, address); |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
return true; |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, |
||||
|
Reg Rn, Reg Rt) { |
||||
|
const bool wback = true; |
||||
|
const bool postindex = !not_postindex; |
||||
|
const size_t scale = size.ZeroExtend<size_t>(); |
||||
|
const u64 offset = imm9.SignExtend<u64>(); |
||||
|
|
||||
|
return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) { |
||||
|
const bool wback = false; |
||||
|
const bool postindex = false; |
||||
|
const size_t scale = size.ZeroExtend<size_t>(); |
||||
|
const u64 offset = imm12.ZeroExtend<u64>() << scale; |
||||
|
|
||||
|
return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) { |
||||
|
const bool wback = false; |
||||
|
const bool postindex = false; |
||||
|
const size_t scale = size.ZeroExtend<size_t>(); |
||||
|
const u64 offset = imm9.SignExtend<u64>(); |
||||
|
|
||||
|
return this->RegisterImmediate(wback, postindex, scale, offset, size, opc, Rn, Rt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::SIMDImmediate(bool wback, bool postindex, size_t scale, u64 offset, |
||||
|
MemOp memop, Reg Rn, Vec Vt) { |
||||
|
const size_t datasize = 8 << scale; |
||||
|
|
||||
|
u64 address; |
||||
|
if (Rn == Reg::SP) { |
||||
|
address = this->GetSp(); |
||||
|
} else { |
||||
|
address = this->GetReg(Rn); |
||||
|
} |
||||
|
|
||||
|
if (!postindex) { |
||||
|
address += offset; |
||||
|
} |
||||
|
|
||||
|
switch (memop) { |
||||
|
case MemOp::Store: { |
||||
|
u128 data = VectorGetElement(this->GetVec(Vt), datasize); |
||||
|
m_memory.WriteBlock(address, &data, datasize / 8); |
||||
|
break; |
||||
|
} |
||||
|
case MemOp::Load: { |
||||
|
u128 data{}; |
||||
|
m_memory.ReadBlock(address, &data, datasize); |
||||
|
this->SetVec(Vt, data); |
||||
|
break; |
||||
|
} |
||||
|
default: |
||||
|
UNREACHABLE(); |
||||
|
} |
||||
|
|
||||
|
if (wback) { |
||||
|
if (postindex) { |
||||
|
address += offset; |
||||
|
} |
||||
|
|
||||
|
if (Rn == Reg::SP) { |
||||
|
this->SetSp(address); |
||||
|
} else { |
||||
|
this->SetReg(Rn, address); |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
return true; |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, |
||||
|
bool not_postindex, Reg Rn, Vec Vt) { |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
|
||||
|
const bool wback = true; |
||||
|
const bool postindex = !not_postindex; |
||||
|
const u64 offset = imm9.SignExtend<u64>(); |
||||
|
|
||||
|
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, |
||||
|
Vec Vt) { |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
|
||||
|
const bool wback = false; |
||||
|
const bool postindex = false; |
||||
|
const u64 offset = imm12.ZeroExtend<u64>() << scale; |
||||
|
|
||||
|
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, |
||||
|
bool not_postindex, Reg Rn, Vec Vt) { |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
|
||||
|
const bool wback = true; |
||||
|
const bool postindex = !not_postindex; |
||||
|
const u64 offset = imm9.SignExtend<u64>(); |
||||
|
|
||||
|
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, |
||||
|
Vec Vt) { |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
|
||||
|
const bool wback = false; |
||||
|
const bool postindex = false; |
||||
|
const u64 offset = imm12.ZeroExtend<u64>() << scale; |
||||
|
|
||||
|
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) { |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
|
||||
|
const bool wback = false; |
||||
|
const bool postindex = false; |
||||
|
const u64 offset = imm9.SignExtend<u64>(); |
||||
|
|
||||
|
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Store, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) { |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
|
||||
|
const bool wback = false; |
||||
|
const bool postindex = false; |
||||
|
const u64 offset = imm9.SignExtend<u64>(); |
||||
|
|
||||
|
return this->SIMDImmediate(wback, postindex, scale, offset, MemOp::Load, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::RegisterOffset(size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1, |
||||
|
Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Reg Rt) { |
||||
|
MemOp memop; |
||||
|
size_t regsize = 64; |
||||
|
bool signed_ = false; |
||||
|
|
||||
|
if (opc_1 == 0) { |
||||
|
memop = opc_0 == 1 ? MemOp::Load : MemOp::Store; |
||||
|
regsize = size == 0b11 ? 64 : 32; |
||||
|
signed_ = false; |
||||
|
} else if (size == 0b11) { |
||||
|
memop = MemOp::Prefetch; |
||||
|
if (opc_0 == 1) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
} else { |
||||
|
memop = MemOp::Load; |
||||
|
if (size == 0b10 && opc_0 == 1) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
regsize = opc_0 == 1 ? 32 : 64; |
||||
|
signed_ = true; |
||||
|
} |
||||
|
|
||||
|
const size_t datasize = 8 << scale; |
||||
|
|
||||
|
// Operation
|
||||
|
const u64 offset = this->ExtendReg(64, Rm, option, shift); |
||||
|
|
||||
|
u64 address; |
||||
|
if (Rn == Reg::SP) { |
||||
|
address = this->GetSp(); |
||||
|
} else { |
||||
|
address = this->GetReg(Rn); |
||||
|
} |
||||
|
address += offset; |
||||
|
|
||||
|
switch (memop) { |
||||
|
case MemOp::Store: { |
||||
|
u64 data = this->GetReg(Rt); |
||||
|
m_memory.WriteBlock(address, &data, datasize / 8); |
||||
|
break; |
||||
|
} |
||||
|
case MemOp::Load: { |
||||
|
u64 data = 0; |
||||
|
m_memory.ReadBlock(address, &data, datasize / 8); |
||||
|
if (signed_) { |
||||
|
this->SetReg(Rt, SignExtend(data, datasize, regsize)); |
||||
|
} else { |
||||
|
this->SetReg(Rt, data); |
||||
|
} |
||||
|
break; |
||||
|
} |
||||
|
case MemOp::Prefetch: |
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
return true; |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, |
||||
|
Reg Rt) { |
||||
|
const Imm<1> opc_0{0}; |
||||
|
const size_t scale = size.ZeroExtend<size_t>(); |
||||
|
const u8 shift = S ? static_cast<u8>(scale) : 0; |
||||
|
if (!option.Bit<1>()) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
return this->RegisterOffset(scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, |
||||
|
Reg Rt) { |
||||
|
const Imm<1> opc_0{1}; |
||||
|
const size_t scale = size.ZeroExtend<size_t>(); |
||||
|
const u8 shift = S ? static_cast<u8>(scale) : 0; |
||||
|
if (!option.Bit<1>()) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
return this->RegisterOffset(scale, shift, size, opc_1, opc_0, Rm, option, Rn, Rt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::SIMDOffset(size_t scale, u8 shift, Imm<1> opc_0, Reg Rm, Imm<3> option, |
||||
|
Reg Rn, Vec Vt) { |
||||
|
const auto memop = opc_0 == 1 ? MemOp::Load : MemOp::Store; |
||||
|
const size_t datasize = 8 << scale; |
||||
|
|
||||
|
// Operation
|
||||
|
const u64 offset = this->ExtendReg(64, Rm, option, shift); |
||||
|
|
||||
|
u64 address; |
||||
|
if (Rn == Reg::SP) { |
||||
|
address = this->GetSp(); |
||||
|
} else { |
||||
|
address = this->GetReg(Rn); |
||||
|
} |
||||
|
address += offset; |
||||
|
|
||||
|
switch (memop) { |
||||
|
case MemOp::Store: { |
||||
|
u128 data = VectorGetElement(this->GetVec(Vt), datasize); |
||||
|
m_memory.WriteBlock(address, &data, datasize / 8); |
||||
|
break; |
||||
|
} |
||||
|
case MemOp::Load: { |
||||
|
u128 data{}; |
||||
|
m_memory.ReadBlock(address, &data, datasize / 8); |
||||
|
this->SetVec(Vt, data); |
||||
|
break; |
||||
|
} |
||||
|
default: |
||||
|
UNREACHABLE(); |
||||
|
} |
||||
|
|
||||
|
return true; |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, |
||||
|
Reg Rn, Vec Vt) { |
||||
|
const Imm<1> opc_0{0}; |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
const u8 shift = S ? static_cast<u8>(scale) : 0; |
||||
|
if (!option.Bit<1>()) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
bool InterpreterVisitor::LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, |
||||
|
Reg Rn, Vec Vt) { |
||||
|
const Imm<1> opc_0{1}; |
||||
|
const size_t scale = Dynarmic::concatenate(opc_1, size).ZeroExtend<size_t>(); |
||||
|
if (scale > 4) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
const u8 shift = S ? static_cast<u8>(scale) : 0; |
||||
|
if (!option.Bit<1>()) { |
||||
|
// Unallocated encoding
|
||||
|
return false; |
||||
|
} |
||||
|
return this->SIMDOffset(scale, shift, opc_0, Rm, option, Rn, Vt); |
||||
|
} |
||||
|
|
||||
|
std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context, |
||||
|
fpsimd_context* fpsimd_context) { |
||||
|
// Construct the interpreter.
|
||||
|
std::span<u64, 31> regs(reinterpret_cast<u64*>(context->regs), 31); |
||||
|
std::span<u128, 32> vregs(reinterpret_cast<u128*>(fpsimd_context->vregs), 32); |
||||
|
u64& sp = *reinterpret_cast<u64*>(&context->sp); |
||||
|
const u64& pc = *reinterpret_cast<u64*>(&context->pc); |
||||
|
|
||||
|
InterpreterVisitor visitor(memory, regs, vregs, sp, pc); |
||||
|
|
||||
|
// Read the instruction at the program counter.
|
||||
|
u32 instruction = memory.Read32(pc); |
||||
|
bool was_executed = false; |
||||
|
|
||||
|
// Interpret the instruction.
|
||||
|
if (auto decoder = Dynarmic::A64::Decode<VisitorBase>(instruction)) { |
||||
|
was_executed = decoder->get().call(visitor, instruction); |
||||
|
} else { |
||||
|
LOG_ERROR(Core_ARM, "Unallocated encoding: {:#x}", instruction); |
||||
|
} |
||||
|
|
||||
|
if (was_executed) { |
||||
|
return pc + 4; |
||||
|
} |
||||
|
|
||||
|
return std::nullopt; |
||||
|
} |
||||
|
|
||||
|
} // namespace Core
|
||||
@ -0,0 +1,103 @@ |
|||||
|
// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project |
||||
|
// SPDX-FileCopyrightText: Copyright 2023 merryhime <https://mary.rs> |
||||
|
// SPDX-License-Identifier: GPL-2.0-or-later |
||||
|
|
||||
|
#pragma once |
||||
|
|
||||
|
#include <signal.h> |
||||
|
#include <unistd.h> |
||||
|
|
||||
|
#include "core/arm/nce/visitor_base.h" |
||||
|
|
||||
|
namespace Core { |
||||
|
|
||||
|
namespace Memory { |
||||
|
class Memory; |
||||
|
} |
||||
|
|
||||
|
class InterpreterVisitor final : public VisitorBase { |
||||
|
public: |
||||
|
explicit InterpreterVisitor(Core::Memory::Memory& memory, std::span<u64, 31> regs, |
||||
|
std::span<u128, 32> fpsimd_regs, u64& sp, const u64& pc) |
||||
|
: m_memory(memory), m_regs(regs), m_fpsimd_regs(fpsimd_regs), m_sp(sp), m_pc(pc) {} |
||||
|
~InterpreterVisitor() override = default; |
||||
|
|
||||
|
enum class MemOp { |
||||
|
Load, |
||||
|
Store, |
||||
|
Prefetch, |
||||
|
}; |
||||
|
|
||||
|
u128 GetVec(Vec v); |
||||
|
u64 GetReg(Reg r); |
||||
|
u64 GetSp(); |
||||
|
u64 GetPc(); |
||||
|
|
||||
|
void SetVec(Vec v, u128 value); |
||||
|
void SetReg(Reg r, u64 value); |
||||
|
void SetSp(u64 value); |
||||
|
|
||||
|
u64 ExtendReg(size_t bitsize, Reg reg, Imm<3> option, u8 shift); |
||||
|
|
||||
|
// Loads and stores - Load/Store Exclusive |
||||
|
bool Ordered(size_t size, bool L, bool o0, Reg Rn, Reg Rt); |
||||
|
bool STLLR(Imm<2> size, Reg Rn, Reg Rt) override; |
||||
|
bool STLR(Imm<2> size, Reg Rn, Reg Rt) override; |
||||
|
bool LDLAR(Imm<2> size, Reg Rn, Reg Rt) override; |
||||
|
bool LDAR(Imm<2> size, Reg Rn, Reg Rt) override; |
||||
|
|
||||
|
// Loads and stores - Load register (literal) |
||||
|
bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) override; |
||||
|
bool LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) override; |
||||
|
|
||||
|
// Loads and stores - Load/Store register pair |
||||
|
bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2, |
||||
|
Reg Rn, Reg Rt) override; |
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bool STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Vec Vt2, |
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Reg Rn, Vec Vt) override; |
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|
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// Loads and stores - Load/Store register (immediate) |
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|
bool RegisterImmediate(bool wback, bool postindex, size_t scale, u64 offset, Imm<2> size, |
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Imm<2> opc, Reg Rn, Reg Rt); |
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bool STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, Reg Rn, |
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|
Reg Rt) override; |
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|
bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) override; |
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|
bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) override; |
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|
||||
|
bool SIMDImmediate(bool wback, bool postindex, size_t scale, u64 offset, MemOp memop, Reg Rn, |
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|
Vec Vt); |
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|
bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, |
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|
Vec Vt) override; |
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|
bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override; |
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|
bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, |
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|
Vec Vt) override; |
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|
bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override; |
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|
bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override; |
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|
bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override; |
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|
|
||||
|
// Loads and stores - Load/Store register (register offset) |
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|
bool RegisterOffset(size_t scale, u8 shift, Imm<2> size, Imm<1> opc_1, Imm<1> opc_0, Reg Rm, |
||||
|
Imm<3> option, Reg Rn, Reg Rt); |
||||
|
bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, |
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|
Reg Rt) override; |
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|
bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, |
||||
|
Reg Rt) override; |
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|
|
||||
|
bool SIMDOffset(size_t scale, u8 shift, Imm<1> opc_0, Reg Rm, Imm<3> option, Reg Rn, Vec Vt); |
||||
|
bool STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, |
||||
|
Vec Vt) override; |
||||
|
bool LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, |
||||
|
Vec Vt) override; |
||||
|
|
||||
|
private: |
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|
Core::Memory::Memory& m_memory; |
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|
std::span<u64, 31> m_regs; |
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|
std::span<u128, 32> m_fpsimd_regs; |
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|
u64& m_sp; |
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|
const u64& m_pc; |
||||
|
}; |
||||
|
|
||||
|
std::optional<u64> MatchAndExecuteOneInstruction(Core::Memory::Memory& memory, mcontext_t* context, |
||||
|
fpsimd_context* fpsimd_context); |
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|
|
||||
|
} // namespace Core |
||||
2777
src/core/arm/nce/visitor_base.h
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