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@ -218,6 +218,9 @@ GraphicsPipeline::GraphicsPipeline(Tegra::Engines::Maxwell3D& maxwell3d_, |
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update_descriptor_queue{update_descriptor_queue_}, spv_modules{std::move(stages)} { |
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std::ranges::transform(infos, stage_infos.begin(), |
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[](const Shader::Info* info) { return info ? *info : Shader::Info{}; }); |
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std::ranges::transform(infos, enabled_uniform_buffers.begin(), [](const Shader::Info* info) { |
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return info ? info->constant_buffer_mask : 0; |
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}); |
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auto func{[this, &render_pass_cache, &descriptor_pool] { |
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DescriptorLayoutBuilder builder{MakeBuilder(device, stage_infos)}; |
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@ -259,11 +262,12 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) { |
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texture_cache.SynchronizeGraphicsDescriptors(); |
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buffer_cache.SetEnabledUniformBuffers(enabled_uniform_buffers); |
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const auto& regs{maxwell3d.regs}; |
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const bool via_header_index{regs.sampler_index == Maxwell::SamplerIndex::ViaHeaderIndex}; |
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const auto config_stage{[&](size_t stage) LAMBDA_FORCEINLINE { |
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const Shader::Info& info{stage_infos[stage]}; |
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buffer_cache.SetEnabledUniformBuffers(stage, info.constant_buffer_mask); |
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buffer_cache.UnbindGraphicsStorageBuffers(stage); |
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if constexpr (Spec::has_storage_buffers) { |
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size_t ssbo_index{}; |
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