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@ -101,13 +101,12 @@ template<> |
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void EmitIR<IR::Opcode::A64SetW>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) { |
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void EmitIR<IR::Opcode::A64SetW>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) { |
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auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(1)); |
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auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(1)); |
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if (inst->GetArg(0).GetType() == IR::Type::A64Reg) { |
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if (inst->GetArg(0).GetType() == IR::Type::A64Reg) { |
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auto const addr = ctx.reg_alloc.ScratchGpr(); |
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auto const tmp = ctx.reg_alloc.ScratchGpr(); |
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auto const tmp = ctx.reg_alloc.ScratchGpr(); |
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auto const offs = offsetof(A64JitState, regs) |
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auto const offs = offsetof(A64JitState, regs) |
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+ A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64); |
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+ A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64); |
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code.MR(tmp, value); |
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code.MR(tmp, value); |
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code.RLDICL(tmp, tmp, 0, 32); |
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code.RLDICL(tmp, tmp, 0, 32); |
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code.STD(tmp, addr, offs); |
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code.STD(tmp, PPC64::RJIT, offs); |
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} else { |
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} else { |
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ASSERT(false && "unimp"); |
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ASSERT(false && "unimp"); |
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} |
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} |
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@ -117,10 +116,9 @@ template<> |
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void EmitIR<IR::Opcode::A64SetX>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) { |
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void EmitIR<IR::Opcode::A64SetX>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) { |
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auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(1)); |
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auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(1)); |
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if (inst->GetArg(0).GetType() == IR::Type::A64Reg) { |
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if (inst->GetArg(0).GetType() == IR::Type::A64Reg) { |
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auto const addr = ctx.reg_alloc.ScratchGpr(); |
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auto const offs = offsetof(A64JitState, regs) |
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auto const offs = offsetof(A64JitState, regs) |
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+ A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64); |
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+ A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64); |
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code.STD(value, addr, offs); |
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code.STD(value, PPC64::RJIT, offs); |
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} else { |
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} else { |
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ASSERT(false && "unimp"); |
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ASSERT(false && "unimp"); |
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} |
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} |
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