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@ -27,29 +27,26 @@ using Tegra::Shader::StoreType; |
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namespace { |
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namespace { |
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Node GetAtomOperation(AtomicOp op, bool is_signed, Node memory, Node data) { |
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const OperationCode operation_code = [op] { |
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switch (op) { |
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case AtomicOp::Add: |
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return OperationCode::AtomicIAdd; |
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case AtomicOp::Min: |
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return OperationCode::AtomicIMin; |
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case AtomicOp::Max: |
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return OperationCode::AtomicIMax; |
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case AtomicOp::And: |
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return OperationCode::AtomicIAnd; |
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case AtomicOp::Or: |
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return OperationCode::AtomicIOr; |
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case AtomicOp::Xor: |
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return OperationCode::AtomicIXor; |
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case AtomicOp::Exch: |
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return OperationCode::AtomicIExchange; |
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default: |
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UNIMPLEMENTED_MSG("op={}", static_cast<int>(op)); |
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return OperationCode::AtomicIAdd; |
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} |
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}(); |
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return SignedOperation(operation_code, is_signed, std::move(memory), std::move(data)); |
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OperationCode GetAtomOperation(AtomicOp op) { |
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switch (op) { |
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case AtomicOp::Add: |
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return OperationCode::AtomicIAdd; |
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case AtomicOp::Min: |
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return OperationCode::AtomicIMin; |
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case AtomicOp::Max: |
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return OperationCode::AtomicIMax; |
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case AtomicOp::And: |
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return OperationCode::AtomicIAnd; |
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case AtomicOp::Or: |
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return OperationCode::AtomicIOr; |
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case AtomicOp::Xor: |
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return OperationCode::AtomicIXor; |
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case AtomicOp::Exch: |
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return OperationCode::AtomicIExchange; |
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default: |
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UNIMPLEMENTED_MSG("op={}", static_cast<int>(op)); |
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return OperationCode::AtomicIAdd; |
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} |
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} |
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} |
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bool IsUnaligned(Tegra::Shader::UniformType uniform_type) { |
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bool IsUnaligned(Tegra::Shader::UniformType uniform_type) { |
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@ -392,7 +389,9 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) { |
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instr.atom.operation == AtomicOp::SafeAdd, |
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instr.atom.operation == AtomicOp::SafeAdd, |
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"operation={}", static_cast<int>(instr.atom.operation.Value())); |
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"operation={}", static_cast<int>(instr.atom.operation.Value())); |
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UNIMPLEMENTED_IF_MSG(instr.atom.type == GlobalAtomicType::S64 || |
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UNIMPLEMENTED_IF_MSG(instr.atom.type == GlobalAtomicType::S64 || |
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instr.atom.type == GlobalAtomicType::U64, |
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instr.atom.type == GlobalAtomicType::U64 || |
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instr.atom.type == GlobalAtomicType::F16x2_FTZ_RN || |
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instr.atom.type == GlobalAtomicType::F32_FTZ_RN, |
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"type={}", static_cast<int>(instr.atom.type.Value())); |
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"type={}", static_cast<int>(instr.atom.type.Value())); |
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const auto [real_address, base_address, descriptor] = |
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const auto [real_address, base_address, descriptor] = |
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@ -403,11 +402,11 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) { |
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} |
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} |
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const bool is_signed = |
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const bool is_signed = |
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instr.atoms.type == AtomicType::S32 || instr.atoms.type == AtomicType::S64; |
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instr.atom.type == GlobalAtomicType::S32 || instr.atom.type == GlobalAtomicType::S64; |
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Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor); |
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Node gmem = MakeNode<GmemNode>(real_address, base_address, descriptor); |
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Node value = GetAtomOperation(static_cast<AtomicOp>(instr.atom.operation), is_signed, gmem, |
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GetRegister(instr.gpr20)); |
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SetRegister(bb, instr.gpr0, std::move(value)); |
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SetRegister(bb, instr.gpr0, |
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SignedOperation(GetAtomOperation(instr.atom.operation), is_signed, gmem, |
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GetRegister(instr.gpr20))); |
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break; |
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break; |
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} |
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} |
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case OpCode::Id::ATOMS: { |
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case OpCode::Id::ATOMS: { |
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@ -422,10 +421,9 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) { |
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const s32 offset = instr.atoms.GetImmediateOffset(); |
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const s32 offset = instr.atoms.GetImmediateOffset(); |
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Node address = GetRegister(instr.gpr8); |
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Node address = GetRegister(instr.gpr8); |
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address = Operation(OperationCode::IAdd, std::move(address), Immediate(offset)); |
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address = Operation(OperationCode::IAdd, std::move(address), Immediate(offset)); |
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Node value = |
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GetAtomOperation(static_cast<AtomicOp>(instr.atoms.operation), is_signed, |
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GetSharedMemory(std::move(address)), GetRegister(instr.gpr20)); |
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SetRegister(bb, instr.gpr0, std::move(value)); |
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SetRegister(bb, instr.gpr0, |
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SignedOperation(GetAtomOperation(instr.atoms.operation), is_signed, |
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GetSharedMemory(std::move(address)), GetRegister(instr.gpr20))); |
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break; |
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break; |
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} |
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} |
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case OpCode::Id::AL2P: { |
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case OpCode::Id::AL2P: { |
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