eden-emu
/
eden
mirror of https://git.eden-emu.dev/eden-emu/eden.git
1
0
Fork 0
Code Releases Wiki Activity
Browse Source

asserts with line info :) 

Signed-off-by: lizzie <lizzie@eden-emu.dev>
pull/2890/head
lizzie 3 months ago
parent
89c0c29c77
commit
e2d5d7e55f
No known key found for this signature in database GPG Key ID: 287378CADCAB13
13 changed files with 74 additions and 76 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 2
      src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
  2. 6
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
  3. 2
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
  4. 36
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
  5. 8
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
  6. 36
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
  7. 20
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
  8. 22
      src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
  9. 2
      src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp
  10. 2
      src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
  11. 2
      src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
  12. 8
      src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
  13. 4
      src/dynarmic/src/dynarmic/common/assert.h

2
src/dynarmic/src/dynarmic/backend/arm64/address_space.cpp
View File

@ -258,7 +258,7 @@ void AddressSpace::Link(EmittedBlockInfo& block_info) {
c.BL(prelude_info.get_ticks_remaining);
break;
default:
ASSERT(false && "Invalid relocation target");
UNREACHABLE();
}
}

6
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64.cpp
View File

@ -112,8 +112,7 @@ void EmitIR<IR::Opcode::GetNZCVFromOp>(oaknut::CodeGenerator& code, EmitContext&
break;
}
default:
ASSERT(false && "Invalid type for GetNZCVFromOp");
break;
UNREACHABLE();
}
}
@ -143,8 +142,7 @@ void EmitIR<IR::Opcode::GetNZFromOp>(oaknut::CodeGenerator& code, EmitContext& c
break;
}
default:
ASSERT(false && "Invalid type for GetNZFromOp");
break;
UNREACHABLE();
}
}

2
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_cryptography.cpp
View File

@ -117,7 +117,7 @@ void EmitIR<IR::Opcode::SM4AccessSubstitutionBox>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>

36
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_floating_point.cpp
View File

@ -123,7 +123,7 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
code.FCVTAS(Rto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
ASSERT(false && "Unimplemented");
UNREACHABLE();
break;
default:
ASSERT(false && "Invalid RoundingMode");
@ -147,7 +147,7 @@ static void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst*
code.FCVTAU(Rto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
ASSERT(false && "Unimplemented");
UNREACHABLE();
break;
default:
ASSERT(false && "Invalid RoundingMode");
@ -188,7 +188,7 @@ void EmitIR<IR::Opcode::FPAbs16>(oaknut::CodeGenerator& code, EmitContext& ctx,
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -315,7 +315,7 @@ void EmitIR<IR::Opcode::FPMulAdd16>(oaknut::CodeGenerator& code, EmitContext& ct
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -333,7 +333,7 @@ void EmitIR<IR::Opcode::FPMulSub16>(oaknut::CodeGenerator& code, EmitContext& ct
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -361,7 +361,7 @@ void EmitIR<IR::Opcode::FPNeg16>(oaknut::CodeGenerator& code, EmitContext& ctx,
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -379,7 +379,7 @@ void EmitIR<IR::Opcode::FPRecipEstimate16>(oaknut::CodeGenerator& code, EmitCont
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -397,7 +397,7 @@ void EmitIR<IR::Opcode::FPRecipExponent16>(oaknut::CodeGenerator& code, EmitCont
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -415,7 +415,7 @@ void EmitIR<IR::Opcode::FPRecipStepFused16>(oaknut::CodeGenerator& code, EmitCon
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -433,7 +433,7 @@ void EmitIR<IR::Opcode::FPRoundInt16>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -515,7 +515,7 @@ void EmitIR<IR::Opcode::FPRSqrtEstimate16>(oaknut::CodeGenerator& code, EmitCont
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -533,7 +533,7 @@ void EmitIR<IR::Opcode::FPRSqrtStepFused16>(oaknut::CodeGenerator& code, EmitCon
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -647,7 +647,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS16>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -655,7 +655,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS32>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -663,7 +663,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedS64>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -671,7 +671,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU16>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -679,7 +679,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU32>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -687,7 +687,7 @@ void EmitIR<IR::Opcode::FPHalfToFixedU64>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>

8
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_memory.cpp
View File

@ -315,7 +315,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.DMB(oaknut::BarrierOp::ISH);
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
} else {
fastmem_location = code.xptr<CodePtr>();
@ -337,7 +337,7 @@ CodePtr EmitMemoryLdr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.LDR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
}
@ -376,7 +376,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.DMB(oaknut::BarrierOp::ISH);
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
} else {
fastmem_location = code.xptr<CodePtr>();
@ -398,7 +398,7 @@ CodePtr EmitMemoryStr(oaknut::CodeGenerator& code, int value_idx, oaknut::XReg X
code.STR(oaknut::QReg{value_idx}, Xbase, Roffset, index_ext);
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
}

36
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_saturation.cpp
View File

@ -131,7 +131,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd8>(oaknut::CodeGenerator& code, EmitCo
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -139,7 +139,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd16>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -147,7 +147,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd32>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -155,7 +155,7 @@ void EmitIR<IR::Opcode::SignedSaturatedAdd64>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -163,7 +163,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh16>(oaknut::Cod
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -171,7 +171,7 @@ void EmitIR<IR::Opcode::SignedSaturatedDoublingMultiplyReturnHigh32>(oaknut::Cod
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -179,7 +179,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub8>(oaknut::CodeGenerator& code, EmitCo
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -187,7 +187,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub16>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -195,7 +195,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub32>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -203,7 +203,7 @@ void EmitIR<IR::Opcode::SignedSaturatedSub64>(oaknut::CodeGenerator& code, EmitC
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -211,7 +211,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd8>(oaknut::CodeGenerator& code, Emit
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -219,7 +219,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd16>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -227,7 +227,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd32>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -235,7 +235,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedAdd64>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -243,7 +243,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub8>(oaknut::CodeGenerator& code, Emit
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -251,7 +251,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub16>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -259,7 +259,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub32>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -267,7 +267,7 @@ void EmitIR<IR::Opcode::UnsignedSaturatedSub64>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
} // namespace Dynarmic::Backend::Arm64

20
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector.cpp
View File

@ -638,7 +638,7 @@ void EmitIR<IR::Opcode::VectorEqual128>(oaknut::CodeGenerator& code, EmitContext
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -867,7 +867,7 @@ void EmitIR<IR::Opcode::VectorMaxS64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -890,7 +890,7 @@ void EmitIR<IR::Opcode::VectorMaxU64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -913,7 +913,7 @@ void EmitIR<IR::Opcode::VectorMinS64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -936,7 +936,7 @@ void EmitIR<IR::Opcode::VectorMinU64>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -1383,7 +1383,7 @@ void EmitIR<IR::Opcode::VectorSignExtend64>(oaknut::CodeGenerator& code, EmitCon
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -1406,7 +1406,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply16>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -1414,7 +1414,7 @@ void EmitIR<IR::Opcode::VectorSignedMultiply32>(oaknut::CodeGenerator& code, Emi
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -1778,7 +1778,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply16>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -1786,7 +1786,7 @@ void EmitIR<IR::Opcode::VectorUnsignedMultiply32>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>

22
src/dynarmic/src/dynarmic/backend/arm64/emit_arm64_vector_floating_point.cpp
View File

@ -227,7 +227,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
code.FCVTAS(Vto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
ASSERT(false && "Unimplemented");
UNREACHABLE();
break;
default:
ASSERT(false && "Invalid RoundingMode");
@ -251,7 +251,7 @@ void EmitToFixed(oaknut::CodeGenerator& code, EmitContext& ctx, IR::Inst* inst)
code.FCVTAU(Vto, Vfrom);
break;
case FP::RoundingMode::ToOdd:
ASSERT(false && "Unimplemented");
UNREACHABLE();
break;
default:
ASSERT(false && "Invalid RoundingMode");
@ -340,7 +340,7 @@ void EmitIR<IR::Opcode::FPVectorEqual16>(oaknut::CodeGenerator& code, EmitContex
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -465,7 +465,7 @@ void EmitIR<IR::Opcode::FPVectorMulAdd16>(oaknut::CodeGenerator& code, EmitConte
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -493,7 +493,7 @@ void EmitIR<IR::Opcode::FPVectorNeg16>(oaknut::CodeGenerator& code, EmitContext&
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -538,7 +538,7 @@ void EmitIR<IR::Opcode::FPVectorRecipEstimate16>(oaknut::CodeGenerator& code, Em
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -556,7 +556,7 @@ void EmitIR<IR::Opcode::FPVectorRecipStepFused16>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -699,7 +699,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtEstimate16>(oaknut::CodeGenerator& code, Em
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -717,7 +717,7 @@ void EmitIR<IR::Opcode::FPVectorRSqrtStepFused16>(oaknut::CodeGenerator& code, E
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -772,7 +772,7 @@ void EmitIR<IR::Opcode::FPVectorToSignedFixed16>(oaknut::CodeGenerator& code, Em
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>
@ -790,7 +790,7 @@ void EmitIR<IR::Opcode::FPVectorToUnsignedFixed16>(oaknut::CodeGenerator& code,
(void)code;
(void)ctx;
(void)inst;
ASSERT(false && "Unimplemented");
UNREACHABLE();
}
template<>

2
src/dynarmic/src/dynarmic/backend/exception_handler_posix.cpp
View File

@ -139,7 +139,7 @@ void SigHandler::SigAction(int sig, siginfo_t* info, void* raw_context) {
}
fmt::print(stderr, "Unhandled {} at pc {:#018x}\n", sig == SIGSEGV ? "SIGSEGV" : "SIGBUS", CTX_PC);
#elif defined(ARCHITECTURE_riscv64)
ASSERT(false && "Unimplemented");
UNREACHABLE();
#else
# error "Invalid architecture"
#endif

2
src/dynarmic/src/dynarmic/backend/riscv64/a32_address_space.cpp
View File

@ -128,7 +128,7 @@ void A32AddressSpace::Link(EmittedBlockInfo& block_info) {
break;
}
default:
ASSERT(false && "Invalid relocation target");
UNREACHABLE();
}
}
}

2
src/dynarmic/src/dynarmic/backend/riscv64/a32_interface.cpp
View File

@ -121,7 +121,7 @@ struct Jit::Impl final {
private:
void RequestCacheInvalidation() {
// ASSERT(false && "Unimplemented");
// UNREACHABLE();
invalidate_entire_cache = false;
invalid_cache_ranges.clear();

8
src/dynarmic/src/dynarmic/backend/x64/emit_x64_memory.h
View File

@ -243,7 +243,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
}
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
return fastmem_location;
} else {
@ -265,7 +265,7 @@ const void* EmitReadMemoryMov(BlockOfCode& code, int value_idx, const Xbyak::Reg
code.movups(Xbyak::Xmm(value_idx), xword[addr]);
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
return fastmem_location;
}
@ -311,7 +311,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
break;
}
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
return fastmem_location;
} else {
@ -333,7 +333,7 @@ const void* EmitWriteMemoryMov(BlockOfCode& code, const Xbyak::RegExp& addr, int
code.movups(xword[addr], Xbyak::Xmm(value_idx));
break;
default:
ASSERT(false && "Invalid bitsize");
UNREACHABLE();
}
return fastmem_location;
}

4
src/dynarmic/src/dynarmic/common/assert.h
View File

@ -8,11 +8,11 @@
[[noreturn]] void assert_terminate_impl(const char* s);
#ifndef ASSERT
# define ASSERT(expr) do if(!(expr)) [[unlikely]] assert_terminate_impl(#expr); while(0)
# define ASSERT(expr) do if(!(expr)) [[unlikely]] assert_terminate_impl(__FILE__ ":" #__LINE__ ": " #expr); while(0)
#endif
#ifndef UNREACHABLE
# ifdef _MSC_VER
# define UNREACHABLE() ASSERT_FALSE("unreachable")
# define UNREACHABLE() ASSERT(false && __FILE__ ":" #__LINE__ ": unreachable")
# else
# define UNREACHABLE() __builtin_unreachable();
# endif

Write Preview
Loading…
Cancel
Save