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@ -34,10 +34,11 @@ u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) { |
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} |
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}(); |
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const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8; |
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switch (opcode->get().GetId()) { |
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case OpCode::Id::R2P_IMM: { |
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const Node mask = GetRegister(instr.gpr8); |
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const auto offset = static_cast<u32>(instr.p2r_r2p.byte) * 8; |
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) { |
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const auto shift = static_cast<u32>(pred); |
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@ -55,6 +56,19 @@ u32 ShaderIR::DecodeRegisterSetPredicate(NodeBlock& bb, u32 pc) { |
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} |
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break; |
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} |
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case OpCode::Id::P2R_IMM: { |
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Node value = Immediate(0); |
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for (u64 pred = 0; pred < NUM_PROGRAMMABLE_PREDICATES; ++pred) { |
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Node bit = Operation(OperationCode::Select, GetPredicate(pred), Immediate(1U << pred), |
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Immediate(0)); |
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value = Operation(OperationCode::UBitwiseOr, std::move(value), std::move(bit)); |
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} |
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value = Operation(OperationCode::UBitwiseAnd, std::move(value), apply_mask); |
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value = BitfieldInsert(GetRegister(instr.gpr8), std::move(value), offset, 8); |
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SetRegister(bb, instr.gpr0, std::move(value)); |
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break; |
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} |
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default: |
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UNIMPLEMENTED_MSG("Unhandled P2R/R2R instruction: {}", opcode->get().GetName()); |
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break; |
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