diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/a32_core.h b/src/dynarmic/src/dynarmic/backend/ppc64/a32_core.h
index 2f051ab5e7..51309df704 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/a32_core.h
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/a32_core.h
@@ -16,8 +16,8 @@
 namespace Dynarmic::Backend::PPC64 {
 
 struct A32JitState {
-    alignas(16) std::array<u32, 64> ext_regs{};
     std::array<u32, 16> regs{};
+    alignas(16) std::array<u32, 64> ext_regs{};
     u32 upper_location_descriptor;
     u32 exclusive_state = 0;
     u32 cpsr_nzcv = 0;
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/a64_core.h b/src/dynarmic/src/dynarmic/backend/ppc64/a64_core.h
index 2ed033323b..5943072413 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/a64_core.h
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/a64_core.h
@@ -18,10 +18,10 @@ namespace Dynarmic::Backend::PPC64 {
 
 struct A64JitState {
     using ProgramCounterType = u32;
-    alignas(16) std::array<u64, 64> vec{};
     std::array<u64, 31> regs{};
-    u64 sp = 0;
     u64 pc = 0;
+    alignas(16) std::array<u64, 64> vec{};
+    u64 sp = 0;
     u32 upper_location_descriptor;
     u32 exclusive_state = 0;
     u32 cpsr_nzcv = 0;
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
index c71b0c1a5a..5c8902924e 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
@@ -191,6 +191,7 @@ EmittedBlockInfo EmitPPC64(powah::Context& code, IR::Block block, const EmitConf
     */
     static FILE* fp = fopen("test.bin", "wb");
     fwrite(code.base, code.offset - start_offset, sizeof(uint32_t), fp);
+    fflush(fp);
 
     ebi.size = code.offset - start_offset;
     return ebi;
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
index fef31c9de6..d446daa0a1 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
@@ -102,8 +102,12 @@ void EmitIR<IR::Opcode::A64SetW>(powah::Context& code, EmitContext& ctx, IR::Ins
     auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(1));
     if (inst->GetArg(0).GetType() == IR::Type::A64Reg) {
         auto const addr = ctx.reg_alloc.ScratchGpr();
-        code.ADDI(addr, PPC64::RJIT, A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64));
-        code.STD(value, addr, offsetof(A64JitState, regs));
+        auto const tmp = ctx.reg_alloc.ScratchGpr();
+        auto const offs = offsetof(A64JitState, regs)
+            + A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64);
+        code.MR(tmp, value);
+        code.RLDICL(tmp, tmp, 0, 32);
+        code.STD(tmp, addr, offs);
     } else {
         ASSERT(false && "unimp");
     }
@@ -114,8 +118,9 @@ void EmitIR<IR::Opcode::A64SetX>(powah::Context& code, EmitContext& ctx, IR::Ins
     auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(1));
     if (inst->GetArg(0).GetType() == IR::Type::A64Reg) {
         auto const addr = ctx.reg_alloc.ScratchGpr();
-        code.ADDI(addr, PPC64::RJIT, A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64));
-        code.STD(value, addr, offsetof(A64JitState, regs));
+        auto const offs = offsetof(A64JitState, regs)
+            + A64::RegNumber(inst->GetArg(0).GetA64RegRef()) * sizeof(u64);
+        code.STD(value, addr, offs);
     } else {
         ASSERT(false && "unimp");
     }