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@ -4,28 +4,12 @@ |
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#pragma once |
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#include <array> |
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#include <atomic> |
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#include <condition_variable> |
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#include <list> |
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#include <memory> |
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#include <mutex> |
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#include "common/bit_field.h" |
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#include "common/common_types.h" |
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#include "core/hle/service/nvdrv/nvdata.h" |
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#include "core/hle/service/nvflinger/buffer_queue.h" |
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#include "video_core/cdma_pusher.h" |
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#include "video_core/dma_pusher.h" |
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#include "video_core/framebuffer_config.h" |
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#include "video_core/gpu_thread.h" |
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using CacheAddr = std::uintptr_t; |
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[[nodiscard]] inline CacheAddr ToCacheAddr(const void* host_ptr) { |
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return reinterpret_cast<CacheAddr>(host_ptr); |
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} |
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[[nodiscard]] inline u8* FromCacheAddr(CacheAddr cache_addr) { |
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return reinterpret_cast<u8*>(cache_addr); |
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} |
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namespace Core { |
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namespace Frontend { |
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@ -40,6 +24,9 @@ class ShaderNotify; |
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} // namespace VideoCore |
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namespace Tegra { |
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class DmaPusher; |
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class CDmaPusher; |
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struct CommandList; |
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enum class RenderTargetFormat : u32 { |
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NONE = 0x0, |
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@ -138,7 +125,18 @@ public: |
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} |
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}; |
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explicit GPU(Core::System& system_, bool is_async_, bool use_nvdec_); |
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enum class FenceOperation : u32 { |
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Acquire = 0, |
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Increment = 1, |
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}; |
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union FenceAction { |
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u32 raw; |
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BitField<0, 1, FenceOperation> op; |
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BitField<8, 24, u32> syncpoint_id; |
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}; |
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explicit GPU(Core::System& system, bool is_async, bool use_nvdec); |
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~GPU(); |
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/// Binds a renderer to the GPU. |
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@ -162,9 +160,7 @@ public: |
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[[nodiscard]] u64 RequestFlush(VAddr addr, std::size_t size); |
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/// Obtains current flush request fence id. |
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[[nodiscard]] u64 CurrentFlushRequestFence() const { |
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return current_flush_fence.load(std::memory_order_relaxed); |
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} |
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[[nodiscard]] u64 CurrentFlushRequestFence() const; |
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/// Tick pending requests within the GPU. |
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void TickWork(); |
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@ -200,24 +196,16 @@ public: |
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[[nodiscard]] const Tegra::CDmaPusher& CDmaPusher() const; |
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/// Returns a reference to the underlying renderer. |
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[[nodiscard]] VideoCore::RendererBase& Renderer() { |
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return *renderer; |
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} |
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[[nodiscard]] VideoCore::RendererBase& Renderer(); |
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/// Returns a const reference to the underlying renderer. |
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const { |
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return *renderer; |
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} |
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const; |
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/// Returns a reference to the shader notifier. |
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify() { |
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return *shader_notify; |
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} |
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify(); |
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/// Returns a const reference to the shader notifier. |
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const { |
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return *shader_notify; |
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} |
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const; |
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/// Allows the CPU/NvFlinger to wait on the GPU before presenting a frame. |
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void WaitFence(u32 syncpoint_id, u32 value); |
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@ -232,80 +220,12 @@ public: |
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[[nodiscard]] u64 GetTicks() const; |
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[[nodiscard]] std::unique_lock<std::mutex> LockSync() { |
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return std::unique_lock{sync_mutex}; |
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} |
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[[nodiscard]] bool IsAsync() const { |
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return is_async; |
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} |
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[[nodiscard]] bool IsAsync() const; |
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[[nodiscard]] bool UseNvdec() const { |
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return use_nvdec; |
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} |
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[[nodiscard]] bool UseNvdec() const; |
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void RendererFrameEndNotify(); |
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enum class FenceOperation : u32 { |
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Acquire = 0, |
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Increment = 1, |
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}; |
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union FenceAction { |
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u32 raw; |
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BitField<0, 1, FenceOperation> op; |
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BitField<8, 24, u32> syncpoint_id; |
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[[nodiscard]] static CommandHeader Build(FenceOperation op, u32 syncpoint_id) { |
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FenceAction result{}; |
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result.op.Assign(op); |
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result.syncpoint_id.Assign(syncpoint_id); |
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return {result.raw}; |
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} |
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}; |
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struct Regs { |
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static constexpr size_t NUM_REGS = 0x40; |
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union { |
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struct { |
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INSERT_PADDING_WORDS_NOINIT(0x4); |
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struct { |
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u32 address_high; |
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u32 address_low; |
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[[nodiscard]] GPUVAddr SemaphoreAddress() const { |
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | |
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address_low); |
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} |
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} semaphore_address; |
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u32 semaphore_sequence; |
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u32 semaphore_trigger; |
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INSERT_PADDING_WORDS_NOINIT(0xC); |
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// The pusher and the puller share the reference counter, the pusher only has read |
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// access |
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u32 reference_count; |
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INSERT_PADDING_WORDS_NOINIT(0x5); |
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u32 semaphore_acquire; |
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u32 semaphore_release; |
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u32 fence_value; |
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FenceAction fence_action; |
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INSERT_PADDING_WORDS_NOINIT(0xE2); |
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// Puller state |
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u32 acquire_mode; |
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u32 acquire_source; |
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u32 acquire_active; |
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u32 acquire_timeout; |
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u32 acquire_value; |
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}; |
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std::array<u32, NUM_REGS> reg_array; |
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}; |
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} regs{}; |
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/// Performs any additional setup necessary in order to begin GPU emulation. |
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/// This can be used to launch any necessary threads and register any necessary |
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/// core timing events. |
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@ -338,104 +258,9 @@ public: |
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated |
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void FlushAndInvalidateRegion(VAddr addr, u64 size); |
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protected: |
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void TriggerCpuInterrupt(u32 syncpoint_id, u32 value) const; |
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private: |
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void ProcessBindMethod(const MethodCall& method_call); |
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void ProcessFenceActionMethod(); |
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void ProcessWaitForInterruptMethod(); |
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void ProcessSemaphoreTriggerMethod(); |
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void ProcessSemaphoreRelease(); |
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void ProcessSemaphoreAcquire(); |
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/// Calls a GPU puller method. |
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void CallPullerMethod(const MethodCall& method_call); |
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/// Calls a GPU engine method. |
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void CallEngineMethod(const MethodCall& method_call); |
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/// Calls a GPU engine multivalue method. |
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void CallEngineMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount, |
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u32 methods_pending); |
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/// Determines where the method should be executed. |
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[[nodiscard]] bool ExecuteMethodOnEngine(u32 method); |
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protected: |
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Core::System& system; |
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std::unique_ptr<Tegra::MemoryManager> memory_manager; |
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std::unique_ptr<Tegra::DmaPusher> dma_pusher; |
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std::unique_ptr<Tegra::CDmaPusher> cdma_pusher; |
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std::unique_ptr<VideoCore::RendererBase> renderer; |
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VideoCore::RasterizerInterface* rasterizer = nullptr; |
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const bool use_nvdec; |
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private: |
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/// Mapping of command subchannels to their bound engine ids |
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std::array<EngineID, 8> bound_engines = {}; |
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/// 3D engine |
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std::unique_ptr<Engines::Maxwell3D> maxwell_3d; |
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/// 2D engine |
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std::unique_ptr<Engines::Fermi2D> fermi_2d; |
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/// Compute engine |
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std::unique_ptr<Engines::KeplerCompute> kepler_compute; |
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/// DMA engine |
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std::unique_ptr<Engines::MaxwellDMA> maxwell_dma; |
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/// Inline memory engine |
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std::unique_ptr<Engines::KeplerMemory> kepler_memory; |
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/// Shader build notifier |
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std::unique_ptr<VideoCore::ShaderNotify> shader_notify; |
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/// When true, we are about to shut down emulation session, so terminate outstanding tasks |
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std::atomic_bool shutting_down{}; |
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{}; |
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts; |
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std::mutex sync_mutex; |
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std::mutex device_mutex; |
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std::condition_variable sync_cv; |
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struct FlushRequest { |
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explicit FlushRequest(u64 fence_, VAddr addr_, std::size_t size_) |
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: fence{fence_}, addr{addr_}, size{size_} {} |
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u64 fence; |
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VAddr addr; |
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std::size_t size; |
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}; |
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std::list<FlushRequest> flush_requests; |
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std::atomic<u64> current_flush_fence{}; |
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u64 last_flush_fence{}; |
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std::mutex flush_request_mutex; |
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const bool is_async; |
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VideoCommon::GPUThread::ThreadManager gpu_thread; |
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std::unique_ptr<Core::Frontend::GraphicsContext> cpu_context; |
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struct Impl; |
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std::unique_ptr<Impl> impl; |
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}; |
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#define ASSERT_REG_POSITION(field_name, position) \ |
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static_assert(offsetof(GPU::Regs, field_name) == position * 4, \ |
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"Field " #field_name " has invalid position") |
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ASSERT_REG_POSITION(semaphore_address, 0x4); |
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ASSERT_REG_POSITION(semaphore_sequence, 0x6); |
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ASSERT_REG_POSITION(semaphore_trigger, 0x7); |
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ASSERT_REG_POSITION(reference_count, 0x14); |
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ASSERT_REG_POSITION(semaphore_acquire, 0x1A); |
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ASSERT_REG_POSITION(semaphore_release, 0x1B); |
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ASSERT_REG_POSITION(fence_value, 0x1C); |
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ASSERT_REG_POSITION(fence_action, 0x1D); |
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ASSERT_REG_POSITION(acquire_mode, 0x100); |
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ASSERT_REG_POSITION(acquire_source, 0x101); |
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ASSERT_REG_POSITION(acquire_active, 0x102); |
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ASSERT_REG_POSITION(acquire_timeout, 0x103); |
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ASSERT_REG_POSITION(acquire_value, 0x104); |
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#undef ASSERT_REG_POSITION |
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} // namespace Tegra |
Fernando S
4 years ago