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Partially revert "[NCE] Fix cache invalidation and signal interrupt race condition (#3063)"
This reverts commit e3c942b209.
pull/3190/head
Caio Oliveira
17 hours ago
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GPG Key ID: AAAE6C7FD4186B0C
1 changed files with
2 additions and
15 deletions
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src/core/arm/nce/arm_nce.cpp
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@ -391,28 +391,15 @@ const std::size_t CACHE_PAGE_SIZE = 4096; |
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void ArmNce::ClearInstructionCache() { |
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#ifdef __aarch64__
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// Use IC IALLU to actually invalidate L1 instruction cache
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// Ensure all previous memory operations complete
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asm volatile("dsb ish\n" |
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"ic iallu\n" |
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"dsb ish\n" |
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"isb" ::: "memory"); |
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#endif
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} |
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void ArmNce::InvalidateCacheRange(u64 addr, std::size_t size) { |
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#ifdef ARCHITECTURE_arm64
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// Invalidate instruction cache for specific range instead of full flush
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constexpr u64 cache_line_size = 64; |
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const u64 aligned_addr = addr & ~(cache_line_size - 1); |
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const u64 end_addr = (addr + size + cache_line_size - 1) & ~(cache_line_size - 1); |
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asm volatile("dsb ish" ::: "memory"); |
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for (u64 i = aligned_addr; i < end_addr; i += cache_line_size) { |
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asm volatile("ic ivau, %0" :: "r"(i) : "memory"); |
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} |
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asm volatile("dsb ish\n" |
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"isb" ::: "memory"); |
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#endif
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this->ClearInstructionCache(); |
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} |
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} // namespace Core
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