|
|
@ -144,10 +144,11 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) { |
|
|
case OpCode::Id::RRO_C: |
|
|
case OpCode::Id::RRO_C: |
|
|
case OpCode::Id::RRO_R: |
|
|
case OpCode::Id::RRO_R: |
|
|
case OpCode::Id::RRO_IMM: { |
|
|
case OpCode::Id::RRO_IMM: { |
|
|
|
|
|
LOG_DEBUG(HW_GPU, "(STUBBED) RRO used"); |
|
|
|
|
|
|
|
|
// Currently RRO is only implemented as a register move.
|
|
|
// Currently RRO is only implemented as a register move.
|
|
|
op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b); |
|
|
op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b); |
|
|
SetRegister(bb, instr.gpr0, op_b); |
|
|
SetRegister(bb, instr.gpr0, op_b); |
|
|
LOG_WARNING(HW_GPU, "RRO instruction is incomplete"); |
|
|
|
|
|
break; |
|
|
break; |
|
|
} |
|
|
} |
|
|
default: |
|
|
default: |
|
|
|