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@ -26,7 +26,6 @@ Maxwell3D::Maxwell3D(Core::System& system, VideoCore::RasterizerInterface& raste |
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MemoryManager& memory_manager) |
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MemoryManager& memory_manager) |
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager}, |
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: system{system}, rasterizer{rasterizer}, memory_manager{memory_manager}, |
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macro_interpreter{*this}, upload_state{memory_manager, regs.upload} { |
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macro_interpreter{*this}, upload_state{memory_manager, regs.upload} { |
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InitDirtySettings(); |
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InitializeRegisterDefaults(); |
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InitializeRegisterDefaults(); |
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} |
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} |
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@ -103,164 +102,6 @@ void Maxwell3D::InitializeRegisterDefaults() { |
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mme_inline[MAXWELL3D_REG_INDEX(index_array.count)] = true; |
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mme_inline[MAXWELL3D_REG_INDEX(index_array.count)] = true; |
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} |
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} |
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#define DIRTY_REGS_POS(field_name) static_cast<u8>(offsetof(Maxwell3D::DirtyRegs, field_name))
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void Maxwell3D::InitDirtySettings() { |
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const auto set_block = [this](std::size_t start, std::size_t range, u8 position) { |
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const auto start_itr = dirty_pointers.begin() + start; |
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const auto end_itr = start_itr + range; |
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std::fill(start_itr, end_itr, position); |
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}; |
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dirty.regs.fill(true); |
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// Init Render Targets
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constexpr u32 registers_per_rt = sizeof(regs.rt[0]) / sizeof(u32); |
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constexpr u32 rt_start_reg = MAXWELL3D_REG_INDEX(rt); |
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constexpr u32 rt_end_reg = rt_start_reg + registers_per_rt * 8; |
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u8 rt_dirty_reg = DIRTY_REGS_POS(render_target); |
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for (u32 rt_reg = rt_start_reg; rt_reg < rt_end_reg; rt_reg += registers_per_rt) { |
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set_block(rt_reg, registers_per_rt, rt_dirty_reg); |
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++rt_dirty_reg; |
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} |
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constexpr u32 depth_buffer_flag = DIRTY_REGS_POS(depth_buffer); |
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_enable)] = depth_buffer_flag; |
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_width)] = depth_buffer_flag; |
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dirty_pointers[MAXWELL3D_REG_INDEX(zeta_height)] = depth_buffer_flag; |
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constexpr u32 registers_in_zeta = sizeof(regs.zeta) / sizeof(u32); |
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constexpr u32 zeta_reg = MAXWELL3D_REG_INDEX(zeta); |
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set_block(zeta_reg, registers_in_zeta, depth_buffer_flag); |
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// Init Vertex Arrays
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constexpr u32 vertex_array_start = MAXWELL3D_REG_INDEX(vertex_array); |
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constexpr u32 vertex_array_size = sizeof(regs.vertex_array[0]) / sizeof(u32); |
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constexpr u32 vertex_array_end = vertex_array_start + vertex_array_size * Regs::NumVertexArrays; |
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u8 va_dirty_reg = DIRTY_REGS_POS(vertex_array); |
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u8 vi_dirty_reg = DIRTY_REGS_POS(vertex_instance); |
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for (u32 vertex_reg = vertex_array_start; vertex_reg < vertex_array_end; |
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vertex_reg += vertex_array_size) { |
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set_block(vertex_reg, 3, va_dirty_reg); |
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// The divisor concerns vertex array instances
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dirty_pointers[static_cast<std::size_t>(vertex_reg) + 3] = vi_dirty_reg; |
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++va_dirty_reg; |
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++vi_dirty_reg; |
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} |
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constexpr u32 vertex_limit_start = MAXWELL3D_REG_INDEX(vertex_array_limit); |
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constexpr u32 vertex_limit_size = sizeof(regs.vertex_array_limit[0]) / sizeof(u32); |
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constexpr u32 vertex_limit_end = vertex_limit_start + vertex_limit_size * Regs::NumVertexArrays; |
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va_dirty_reg = DIRTY_REGS_POS(vertex_array); |
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for (u32 vertex_reg = vertex_limit_start; vertex_reg < vertex_limit_end; |
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vertex_reg += vertex_limit_size) { |
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set_block(vertex_reg, vertex_limit_size, va_dirty_reg); |
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va_dirty_reg++; |
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} |
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constexpr u32 vertex_instance_start = MAXWELL3D_REG_INDEX(instanced_arrays); |
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constexpr u32 vertex_instance_size = |
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sizeof(regs.instanced_arrays.is_instanced[0]) / sizeof(u32); |
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constexpr u32 vertex_instance_end = |
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vertex_instance_start + vertex_instance_size * Regs::NumVertexArrays; |
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vi_dirty_reg = DIRTY_REGS_POS(vertex_instance); |
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for (u32 vertex_reg = vertex_instance_start; vertex_reg < vertex_instance_end; |
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vertex_reg += vertex_instance_size) { |
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set_block(vertex_reg, vertex_instance_size, vi_dirty_reg); |
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vi_dirty_reg++; |
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} |
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set_block(MAXWELL3D_REG_INDEX(vertex_attrib_format), regs.vertex_attrib_format.size(), |
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DIRTY_REGS_POS(vertex_attrib_format)); |
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// Init Shaders
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constexpr u32 shader_registers_count = |
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sizeof(regs.shader_config[0]) * Regs::MaxShaderProgram / sizeof(u32); |
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set_block(MAXWELL3D_REG_INDEX(shader_config[0]), shader_registers_count, |
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DIRTY_REGS_POS(shaders)); |
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// State
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// Viewport
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constexpr u8 viewport_dirty_reg = DIRTY_REGS_POS(viewport); |
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constexpr u32 viewport_start = MAXWELL3D_REG_INDEX(viewports); |
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constexpr u32 viewport_size = sizeof(regs.viewports) / sizeof(u32); |
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set_block(viewport_start, viewport_size, viewport_dirty_reg); |
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constexpr u32 view_volume_start = MAXWELL3D_REG_INDEX(view_volume_clip_control); |
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constexpr u32 view_volume_size = sizeof(regs.view_volume_clip_control) / sizeof(u32); |
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set_block(view_volume_start, view_volume_size, viewport_dirty_reg); |
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// Viewport transformation
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constexpr u32 viewport_trans_start = MAXWELL3D_REG_INDEX(viewport_transform); |
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constexpr u32 viewport_trans_size = sizeof(regs.viewport_transform) / sizeof(u32); |
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set_block(viewport_trans_start, viewport_trans_size, DIRTY_REGS_POS(viewport_transform)); |
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// Cullmode
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constexpr u32 cull_mode_start = MAXWELL3D_REG_INDEX(cull); |
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constexpr u32 cull_mode_size = sizeof(regs.cull) / sizeof(u32); |
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set_block(cull_mode_start, cull_mode_size, DIRTY_REGS_POS(cull_mode)); |
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// Screen y control
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dirty_pointers[MAXWELL3D_REG_INDEX(screen_y_control)] = DIRTY_REGS_POS(screen_y_control); |
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// Primitive Restart
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constexpr u32 primitive_restart_start = MAXWELL3D_REG_INDEX(primitive_restart); |
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constexpr u32 primitive_restart_size = sizeof(regs.primitive_restart) / sizeof(u32); |
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set_block(primitive_restart_start, primitive_restart_size, DIRTY_REGS_POS(primitive_restart)); |
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// Depth Test
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constexpr u8 depth_test_dirty_reg = DIRTY_REGS_POS(depth_test); |
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_test_enable)] = depth_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_write_enabled)] = depth_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_test_func)] = depth_test_dirty_reg; |
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// Stencil Test
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constexpr u32 stencil_test_dirty_reg = DIRTY_REGS_POS(stencil_test); |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_enable)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_func_func)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_func_ref)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_func_mask)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_op_fail)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_op_zfail)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_op_zpass)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_front_mask)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_two_side_enable)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_func_func)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_func_ref)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_func_mask)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_op_fail)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_op_zfail)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_op_zpass)] = stencil_test_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(stencil_back_mask)] = stencil_test_dirty_reg; |
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// Color Mask
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constexpr u8 color_mask_dirty_reg = DIRTY_REGS_POS(color_mask); |
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dirty_pointers[MAXWELL3D_REG_INDEX(color_mask_common)] = color_mask_dirty_reg; |
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set_block(MAXWELL3D_REG_INDEX(color_mask), sizeof(regs.color_mask) / sizeof(u32), |
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color_mask_dirty_reg); |
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// Blend State
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constexpr u8 blend_state_dirty_reg = DIRTY_REGS_POS(blend_state); |
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set_block(MAXWELL3D_REG_INDEX(blend_color), sizeof(regs.blend_color) / sizeof(u32), |
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blend_state_dirty_reg); |
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dirty_pointers[MAXWELL3D_REG_INDEX(independent_blend_enable)] = blend_state_dirty_reg; |
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set_block(MAXWELL3D_REG_INDEX(blend), sizeof(regs.blend) / sizeof(u32), blend_state_dirty_reg); |
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set_block(MAXWELL3D_REG_INDEX(independent_blend), sizeof(regs.independent_blend) / sizeof(u32), |
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blend_state_dirty_reg); |
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// Scissor State
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constexpr u8 scissor_test_dirty_reg = DIRTY_REGS_POS(scissor_test); |
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set_block(MAXWELL3D_REG_INDEX(scissor_test), sizeof(regs.scissor_test) / sizeof(u32), |
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scissor_test_dirty_reg); |
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// Polygon Offset
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constexpr u8 polygon_offset_dirty_reg = DIRTY_REGS_POS(polygon_offset); |
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_fill_enable)] = polygon_offset_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_line_enable)] = polygon_offset_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_point_enable)] = polygon_offset_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_units)] = polygon_offset_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_factor)] = polygon_offset_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(polygon_offset_clamp)] = polygon_offset_dirty_reg; |
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// Depth bounds
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constexpr u8 depth_bounds_values_dirty_reg = DIRTY_REGS_POS(depth_bounds_values); |
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_bounds[0])] = depth_bounds_values_dirty_reg; |
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dirty_pointers[MAXWELL3D_REG_INDEX(depth_bounds[1])] = depth_bounds_values_dirty_reg; |
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} |
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void Maxwell3D::CallMacroMethod(u32 method, std::size_t num_parameters, const u32* parameters) { |
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void Maxwell3D::CallMacroMethod(u32 method, std::size_t num_parameters, const u32* parameters) { |
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// Reset the current macro.
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// Reset the current macro.
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executing_macro = 0; |
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executing_macro = 0; |
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@ -317,23 +158,7 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) { |
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ASSERT_MSG(method < Regs::NUM_REGS, |
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ASSERT_MSG(method < Regs::NUM_REGS, |
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"Invalid Maxwell3D register, increase the size of the Regs structure"); |
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"Invalid Maxwell3D register, increase the size of the Regs structure"); |
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if (regs.reg_array[method] != method_call.argument) { |
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regs.reg_array[method] = method_call.argument; |
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const std::size_t dirty_reg = dirty_pointers[method]; |
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if (dirty_reg) { |
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dirty.regs[dirty_reg] = true; |
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if (dirty_reg >= DIRTY_REGS_POS(vertex_array) && |
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dirty_reg < DIRTY_REGS_POS(vertex_array_buffers)) { |
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dirty.vertex_array_buffers = true; |
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} else if (dirty_reg >= DIRTY_REGS_POS(vertex_instance) && |
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dirty_reg < DIRTY_REGS_POS(vertex_instances)) { |
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dirty.vertex_instances = true; |
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} else if (dirty_reg >= DIRTY_REGS_POS(render_target) && |
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dirty_reg < DIRTY_REGS_POS(render_settings)) { |
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dirty.render_settings = true; |
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} |
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} |
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} |
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regs.reg_array[method] = method_call.argument; |
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switch (method) { |
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switch (method) { |
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case MAXWELL3D_REG_INDEX(macros.data): { |
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case MAXWELL3D_REG_INDEX(macros.data): { |
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@ -418,9 +243,6 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) { |
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case MAXWELL3D_REG_INDEX(data_upload): { |
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case MAXWELL3D_REG_INDEX(data_upload): { |
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const bool is_last_call = method_call.IsLastCall(); |
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const bool is_last_call = method_call.IsLastCall(); |
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upload_state.ProcessData(method_call.argument, is_last_call); |
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upload_state.ProcessData(method_call.argument, is_last_call); |
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if (is_last_call) { |
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dirty.OnMemoryWrite(); |
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} |
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break; |
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break; |
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} |
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} |
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default: |
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default: |
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@ -727,7 +549,6 @@ void Maxwell3D::FinishCBData() { |
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const u32 id = cb_data_state.id; |
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const u32 id = cb_data_state.id; |
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memory_manager.WriteBlock(address, cb_data_state.buffer[id].data(), size); |
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memory_manager.WriteBlock(address, cb_data_state.buffer[id].data(), size); |
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dirty.OnMemoryWrite(); |
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cb_data_state.id = null_cb_data; |
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cb_data_state.id = null_cb_data; |
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cb_data_state.current = null_cb_data; |
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cb_data_state.current = null_cb_data; |
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