diff --git a/src/common/vector_math.h b/src/common/vector_math.h
index 6ab58756e5..e2ee88af2d 100644
--- a/src/common/vector_math.h
+++ b/src/common/vector_math.h
@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText: Copyright 2025 Eden Emulator Project
+// SPDX-FileCopyrightText: Copyright 2026 Eden Emulator Project
 // SPDX-License-Identifier: GPL-3.0-or-later
 
 // SPDX-FileCopyrightText: 2014 Tony Wasserka
diff --git a/src/core/arm/nce/arm_nce.cpp b/src/core/arm/nce/arm_nce.cpp
index 01ea36a4fa..6d5675ec85 100644
--- a/src/core/arm/nce/arm_nce.cpp
+++ b/src/core/arm/nce/arm_nce.cpp
@@ -106,6 +106,7 @@ void ArmNce::UnlockThreadParameters(void* tpidr) {
     static_cast<NativeExecutionParameters*>(tpidr)->lock.store(SpinLockUnlocked, std::memory_order_release);
 }
 
+#ifndef __WIN32
 YUZU_NAKED
 YUZU_NO_INLINE
 HaltReason ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void *tpidr) {
@@ -141,6 +142,14 @@ HaltReason ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void *tpidr) {
         );
 }
 YUZU_NAKED_END
+#else
+HaltReason ArmNce::ReturnToRunCodeByExceptionLevelChange(int tid, void *tpidr) {
+    DEBUG_ASSERT(os::TlsGetValue(ContextKey) == tpidr);
+
+    os::RaiseException(SIGUSR2, 0, 0, nullptr); // TODO: pass tpidr through arguments?
+    __builtin_unreachable();
+}
+#endif
 
 void ArmNce::ReturnToRunCodeByExceptionLevelChangeSignalHandler(int sig, void *info, void *raw_context) {
     auto tpidr = static_cast<NativeExecutionParameters*>(RestoreGuestContext(raw_context));
@@ -224,9 +233,11 @@ YUZU_NAKED_END
 
 static_assert(offsetof(HostContext, host_sp) == 0xE0); // TODO: don't use magic number
 
+#ifndef __WIN32
+
 void ArmNce::BreakFromRunCodeSignalHandler(int sig, void *info, void *raw_context) {
-    NativeExecutionParameters* tpidr = reinterpret_cast<NativeExecutionParameters *>(GetGuestParameters());
-#if defined(__APPLE__) || defined(__WIN32)
+    NativeExecutionParameters* tpidr = static_cast<NativeExecutionParameters *>(GetGuestParameters());
+#if defined(__APPLE__)
     if (tpidr->is_actually_running) {
         tpidr->is_actually_running = false;
 #else
@@ -242,6 +253,8 @@ void ArmNce::BreakFromRunCodeSignalHandler(int sig, void *info, void *raw_contex
     }
 }
 
+#endif
+
 void ArmNce::GuestMemoryFaultSignalHandler(int sig, void* raw_info, void* raw_context) {
     DEBUG_ASSERT(sig == SIGSEGV || sig == SIGBUS);
 
@@ -326,8 +339,12 @@ void* ArmNce::RestoreGuestContext(void* raw_context) {
     // Retrieve the host context.
     auto host_ctx = KernelContext(raw_context);
 
+#ifndef __WIN32
     // Thread-local parameters will be located in x9.
     auto* tpidr = reinterpret_cast<NativeExecutionParameters*>(host_ctx.regs()[9]);
+#else
+    auto* tpidr = static_cast<NativeExecutionParameters*>(GetGuestParameters());
+#endif
     auto* guest_ctx = static_cast<GuestContext*>(tpidr->native_context);
 
     // Save host callee-saved registers.
@@ -647,7 +664,8 @@ void ArmNce::SignalInterrupt(Kernel::KThread* thread) {
             "svc #0x80\n"
             :: "r"(static_cast<u64>(m_thread_id)), "r"(static_cast<u64>(SIGURG))
             : "x0", "x1", "x16", "memory", "cc");
-#elif
+#elif defined(__WIN32)
+        // TODO: use SetThreadState to emulate BreakFromRunCodeSignalHandler
         SuspendThread(m_thread_id);
         UnlockThreadParameters(params);
 #endif
diff --git a/src/core/arm/nce/arm_nce.h b/src/core/arm/nce/arm_nce.h
index c643b50e75..aa00a8983f 100644
--- a/src/core/arm/nce/arm_nce.h
+++ b/src/core/arm/nce/arm_nce.h
@@ -33,12 +33,13 @@ constexpr pthread_key_t ContextKey = 210;
 namespace os {
 extern "C" {
     #include <winternl.h>
+    #include <processthreadsapi.h>
+    #include <errhandlingapi.h>
 }
-
 }
 
-static const u32 ContextKey = TlsAlloc();
-static const u32 NCEStorage = TlsAlloc();
+static const u32 ContextKey = os::TlsAlloc();
+static const u32 NCEStorage = os::TlsAlloc();
 static const u64 TlsSlots = offsetof(os::TEB, TlsSlots);
 #endif
 
diff --git a/src/core/arm/nce/guest_context.h b/src/core/arm/nce/guest_context.h
index 59443d808c..d0a35f43d6 100644
--- a/src/core/arm/nce/guest_context.h
+++ b/src/core/arm/nce/guest_context.h
@@ -162,7 +162,7 @@ private:
         return reinterpret_cast<fpsimd_context*>(header);
     }
 #elif defined(__WIN32)
-    ARM64_NT_CONTEXT* ptr;
+    CONTEXT* ptr;
 #endif
 };
 
diff --git a/src/core/arm/nce/patcher.cpp b/src/core/arm/nce/patcher.cpp
index 28c0261a67..9bf2e80681 100644
--- a/src/core/arm/nce/patcher.cpp
+++ b/src/core/arm/nce/patcher.cpp
@@ -17,7 +17,10 @@
 #include "core/hle/kernel/svc.h"
 #include "core/memory.h"
 #include "core/hle/kernel/k_thread.h"
+
+#ifdef __WIN32
 #include "win/platform_visitor.h"
+#endif
 
 namespace Core::NCE {
 
diff --git a/src/core/arm/nce/win/exceptions.h b/src/core/arm/nce/win/exceptions.h
index b6fcc77ac8..e0dc9ca484 100644
--- a/src/core/arm/nce/win/exceptions.h
+++ b/src/core/arm/nce/win/exceptions.h
@@ -8,7 +8,6 @@
 #define SIGBUS EXCEPTION_DATATYPE_MISALIGNMENT
 #define SIGSEGV EXCEPTION_ACCESS_VIOLATION
 #define SIGUSR2 0xE0000001
-#define SIGURG 0xE0000002
 
 namespace Core {
 
diff --git a/src/core/arm/nce/win/platform_visitor.h b/src/core/arm/nce/win/platform_visitor.h
index 8e718cbe5a..458c8a5093 100644
--- a/src/core/arm/nce/win/platform_visitor.h
+++ b/src/core/arm/nce/win/platform_visitor.h
@@ -19,7 +19,7 @@ std::optional<oaknut::Reg> CheckForPlatformRegister(u32 instruction);
 class PlatformVisitor final : public VisitorBase {
 public:
     PlatformVisitor();
-    ~PlatformVisitor() = default;
+    ~PlatformVisitor() override = default;
 
     Reg scratch;
 
@@ -38,1323 +38,1323 @@ public:
         UNREACHABLE();
     }
 
-    bool UnallocatedEncoding() {
+    bool UnallocatedEncoding() override {
         return false;
     }
 
-    bool ADR(Imm<2> immlo, Imm<19> immhi, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool ADR(Imm<2> immlo, Imm<19> immhi, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool ADRP(Imm<2> immlo, Imm<19> immhi, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool ADDG(Imm<6> offset_imm, Imm<4> tag_offset, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ADDG(Imm<6> offset_imm, Imm<4> tag_offset, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SUBG(Imm<6> offset_imm, Imm<4> tag_offset, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SUBG(Imm<6> offset_imm, Imm<4> tag_offset, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ADD_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool ADDS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ADDS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SUB_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SUBS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SUBS_imm(bool sf, Imm<2> shift, Imm<12> imm12, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool AND_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ORR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool EOR_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ANDS_imm(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool MOVN(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool MOVN(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool MOVZ(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool MOVZ(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool MOVK(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool MOVK(bool sf, Imm<2> hw, Imm<16> imm16, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool BFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool UBFM(bool sf, bool N, Imm<6> immr, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool ASR_1(Imm<5> immr, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ASR_1(Imm<5> immr, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool ASR_2(Imm<6> immr, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool ASR_2(Imm<6> immr, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SXTB_1(Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SXTB_1(Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SXTB_2(Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SXTB_2(Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SXTH_1(Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SXTH_1(Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SXTH_2(Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SXTH_2(Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SXTW(Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool SXTW(Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool EXTR(bool sf, bool N, Reg Rm, Imm<6> imms, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool EXTR(bool sf, bool N, Reg Rm, Imm<6> imms, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool XPAC_1(bool D, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool XPAC_1(bool D, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool PACIA_1(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool PACIA_1(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool PACIB_1(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool PACIB_1(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool AUTIA_1(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool AUTIA_1(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool AUTIB_1(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool AUTIB_1(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool SYS(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool SYS(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool MSR_reg(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool SYSL(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool SYSL(Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool MRS(Imm<1> o0, Imm<3> op1, Imm<4> CRn, Imm<4> CRm, Imm<3> op2, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool RMIF(Imm<6> lsb, Reg Rn, Imm<4> mask) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool RMIF(Imm<6> lsb, Reg Rn, Imm<4> mask) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool SETF8(Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool SETF8(Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool SETF16(Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool SETF16(Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool DC_IVAC(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_IVAC(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_ISW(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_ISW(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_CSW(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_CSW(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_CISW(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_CISW(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_ZVA(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_ZVA(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_CVAC(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_CVAC(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_CVAU(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_CVAU(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_CVAP(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_CVAP(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool DC_CIVAC(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool DC_CIVAC(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool IC_IVAU(Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool IC_IVAU(Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool BR(Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool BR(Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool BRA(bool Z, bool M, Reg Rn, Reg Rm) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool BRA(bool Z, bool M, Reg Rn, Reg Rm) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool BLR(Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool BLR(Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool BLRA(bool Z, bool M, Reg Rn, Reg Rm) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool BLRA(bool Z, bool M, Reg Rn, Reg Rm) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool RET(Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool RET(Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool CBZ(bool sf, Imm<19> imm19, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool CBZ(bool sf, Imm<19> imm19, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool CBNZ(bool sf, Imm<19> imm19, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool CBNZ(bool sf, Imm<19> imm19, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool TBZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool TBNZ(Imm<1> b5, Imm<5> b40, Imm<14> imm14, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool STx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool STx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LDx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LDx_mult_1(bool Q, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LDx_mult_2(bool Q, Reg Rm, Imm<4> opcode, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ST1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool ST1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ST3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool ST3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ST2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool ST2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ST4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool ST4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD1_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD1_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD3_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD3_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD1R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD1R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD3R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD3R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD2_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD2_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD4_sngl_1(bool Q, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD4_sngl_2(bool Q, Reg Rm, Imm<2> upper_opcode, bool S, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD2R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD2R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LD4R_1(bool Q, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LD4R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LD4R_2(bool Q, Reg Rm, Imm<2> size, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool STXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool STXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool STLXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool STLXR(Imm<2> size, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool STXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool STXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool STLXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool STLXP(Imm<1> size, Reg Rs, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDXR(Imm<2> size, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDXR(Imm<2> size, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDAXR(Imm<2> size, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDAXR(Imm<2> size, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDAXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDAXP(Imm<1> size, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STLLR(Imm<2> size, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STLLR(Imm<2> size, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STLR(Imm<2> size, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STLR(Imm<2> size, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDLAR(Imm<2> size, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDLAR(Imm<2> size, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDAR(Imm<2> size, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDAR(Imm<2> size, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool CASP(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool CASP(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool CASB(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool CASB(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool CASH(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool CASH(bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool CAS(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool CAS(bool sz, bool L, Reg Rs, bool o0, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool LDR_lit_gen(bool opc_0, Imm<19> imm19, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool LDRSW_lit(Imm<19> imm19, Reg Rt) {
-        ChooseScratch(Reg::X18, Rt);
-        return false || Rt == Reg::X18;
+    bool LDRSW_lit(Imm<19> imm19, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rt);
+        return Rt == Reg::R18;
     }
 
-    bool STNP_LDNP_gen(Imm<1> upper_opc, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STNP_LDNP_gen(Imm<1> upper_opc, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STNP_LDNP_fpsimd(Imm<2> opc, Imm<1> L, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STNP_LDNP_fpsimd(Imm<2> opc, Imm<1> L, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STP_LDP_gen(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STP_LDP_fpsimd(Imm<2> opc, bool not_postindex, bool wback, Imm<1> L, Imm<7> imm7, Vec Vt2, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STGP_1(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STGP_1(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STGP_2(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STGP_2(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STGP_3(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STGP_3(Imm<7> offset_imm, Reg Rt2, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STRx_LDRx_imm_1(Imm<2> size, Imm<2> opc, Imm<9> imm9, bool not_postindex, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STRx_LDRx_imm_2(Imm<2> size, Imm<2> opc, Imm<12> imm12, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STURx_LDURx(Imm<2> size, Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool PRFM_imm(Imm<12> imm12, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool PRFM_imm(Imm<12> imm12, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool PRFM_unscaled_imm(Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool PRFM_unscaled_imm(Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LDR_imm_fpsimd_1(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, bool not_postindex, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LDR_imm_fpsimd_2(Imm<2> size, Imm<1> opc_1, Imm<12> imm12, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool LDUR_fpsimd(Imm<2> size, Imm<1> opc_1, Imm<9> imm9, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STTRB(Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDTRB(Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDTRB(Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDTRSB(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDTRSB(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STTRH(Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDTRH(Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDTRH(Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDTRSH(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDTRSH(Imm<2> opc, Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDTR(Imm<2> size, Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDTRSW(Imm<9> imm9, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDADDB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDADDB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDCLRB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDCLRB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDEORB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDEORB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSETB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSETB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDUMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDUMAXB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDUMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDUMINB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool SWPB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool SWPB(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDAPRB(Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDAPRB(Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDADDH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDADDH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDCLRH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDCLRH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDEORH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDEORH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSETH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSETH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDUMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDUMAXH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDUMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDUMINH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool SWPH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool SWPH(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDAPRH(Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDAPRH(Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDADD(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDADD(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDCLR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDCLR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDEOR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDEOR(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSET(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSET(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDSMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDSMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDUMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDUMAX(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDUMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool LDUMIN(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool SWP(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rs);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rs == Reg::X18;
+    bool SWP(bool A, bool R, Reg Rs, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rs);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rs == Reg::R18;
     }
 
-    bool LDAPR(Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDAPR(Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rm);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rm == Reg::X18;
+    bool STRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rm);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt, Rm);
-        return false || Rn == Reg::X18 || Rt == Reg::X18 || Rm == Reg::X18;
+    bool LDRx_reg(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt, Rm);
+        return Rn == Reg::R18 || Rt == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool STR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool LDR_reg_fpsimd(Imm<2> size, Imm<1> opc_1, Reg Rm, Imm<3> option, bool S, Reg Rn, Vec Vt) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool STG_1(Imm<9> imm9, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STG_1(Imm<9> imm9, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STG_2(Imm<9> imm9, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STG_2(Imm<9> imm9, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STG_3(Imm<9> imm9, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STG_3(Imm<9> imm9, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LDG(Imm<9> offset_imm, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDG(Imm<9> offset_imm, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STZG_1(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STZG_1(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STZG_2(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STZG_2(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STZG_3(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STZG_3(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST2G_1(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST2G_1(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST2G_2(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST2G_2(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool ST2G_3(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool ST2G_3(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STGV(Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool STGV(Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool STZ2G_1(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STZ2G_1(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STZ2G_2(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STZ2G_2(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool STZ2G_3(Imm<9> offset_imm, Reg Rn) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool STZ2G_3(Imm<9> offset_imm, Reg Rn) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool LDGV(Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDGV(Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool LDRA(bool M, bool S, Imm<9> imm9, bool W, Reg Rn, Reg Rt) {
-        ChooseScratch(Reg::X18, Rn, Rt);
-        return false || Rn == Reg::X18 || Rt == Reg::X18;
+    bool LDRA(bool M, bool S, Imm<9> imm9, bool W, Reg Rn, Reg Rt) override {
+        ChooseScratch(Reg::R18, Rn, Rt);
+        return Rn == Reg::R18 || Rt == Reg::R18;
     }
 
-    bool UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool UDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SDIV(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool LSLV(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool LSRV(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ASRV(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool RORV(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CRC32(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool CRC32(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CRC32C(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool CRC32C(bool sf, Reg Rm, Imm<2> sz, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool PACGA(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool PACGA(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SUBP(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SUBP(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool IRG(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool IRG(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool GMI(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool GMI(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SUBPS(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SUBPS(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool RBIT_int(bool sf, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool RBIT_int(bool sf, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool REV16_int(bool sf, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool REV16_int(bool sf, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool REV(bool sf, bool opc_0, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool REV(bool sf, bool opc_0, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool CLZ_int(bool sf, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool CLZ_int(bool sf, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool CLS_int(bool sf, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool CLS_int(bool sf, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool REV32_int(Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool REV32_int(Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool PACDA(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool PACDA(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool PACDB(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool PACDB(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool AUTDA(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool AUTDA(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool AUTDB(bool Z, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd);
-        return false || Rn == Reg::X18 || Rd == Reg::X18;
+    bool AUTDB(bool Z, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd);
+        return Rn == Reg::R18 || Rd == Reg::R18;
     }
 
-    bool AND_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool AND_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool BIC_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool BIC_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ORR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ORR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ORN_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ORN_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool EOR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool EOR_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool EON(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ANDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ANDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool BICS(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ADD_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ADD_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ADDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ADDS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SUB_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SUB_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SUBS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SUBS_shift(bool sf, Imm<2> shift, Reg Rm, Imm<6> imm6, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ADD_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ADD_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ADDS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ADDS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SUB_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SUB_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SUBS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SUBS_ext(bool sf, Reg Rm, Imm<3> option, Imm<3> imm3, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ADC(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ADC(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool ADCS(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool ADCS(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SBC(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SBC(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SBCS(bool sf, Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CCMN_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool CCMN_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CCMP_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool CCMP_reg(bool sf, Reg Rm, Cond cond, Reg Rn, Imm<4> nzcv) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CCMN_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool CCMN_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool CCMP_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool CCMP_imm(bool sf, Imm<5> imm5, Cond cond, Reg Rn, Imm<4> nzcv) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool CSEL(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool CSEL(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CSINC(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool CSINC(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CSINV(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool CSINV(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool CSNEG(bool sf, Reg Rm, Cond cond, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool MADD(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm, Ra);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18 || Ra == Reg::X18;
+    bool MADD(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm, Ra);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18 || Ra == Reg::R18;
     }
 
-    bool MSUB(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm, Ra);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18 || Ra == Reg::X18;
+    bool MSUB(bool sf, Reg Rm, Reg Ra, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm, Ra);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18 || Ra == Reg::R18;
     }
 
-    bool SMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm, Ra);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18 || Ra == Reg::X18;
+    bool SMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm, Ra);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18 || Ra == Reg::R18;
     }
 
-    bool SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm, Ra);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18 || Ra == Reg::X18;
+    bool SMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm, Ra);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18 || Ra == Reg::R18;
     }
 
-    bool SMULH(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool SMULH(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm, Ra);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18 || Ra == Reg::X18;
+    bool UMADDL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm, Ra);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18 || Ra == Reg::R18;
     }
 
-    bool UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm, Ra);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18 || Ra == Reg::X18;
+    bool UMSUBL(Reg Rm, Reg Ra, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm, Ra);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18 || Ra == Reg::R18;
     }
 
-    bool UMULH(Reg Rm, Reg Rn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rn, Rd, Rm);
-        return false || Rn == Reg::X18 || Rd == Reg::X18 || Rm == Reg::X18;
+    bool UMULH(Reg Rm, Reg Rn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rn, Rd, Rm);
+        return Rn == Reg::R18 || Rd == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SQDMLAL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool SQDMLAL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SQDMLSL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool SQDMLSL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool SQDMULL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn, Rm);
-        return false || Rn == Reg::X18 || Rm == Reg::X18;
+    bool SQDMULL_vec_1(Imm<2> size, Reg Rm, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn, Rm);
+        return Rn == Reg::R18 || Rm == Reg::R18;
     }
 
-    bool DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool DUP_gen(bool Q, Imm<5> imm5, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool SMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool UMOV(bool Q, Imm<5> imm5, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool INS_gen(Imm<5> imm5, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool INS_gen(Imm<5> imm5, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool SCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool UCVTF_float_fix(bool sf, Imm<2> type, Imm<6> scale, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTZS_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTZU_float_fix(bool sf, Imm<2> type, Imm<6> scale, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTNS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTNS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTNU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTNU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool SCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) {
-        ChooseScratch(Reg::X18, Rn);
-        return false || Rn == Reg::X18;
+    bool UCVTF_float_int(bool sf, Imm<2> type, Reg Rn, Vec Vd) override {
+        ChooseScratch(Reg::R18, Rn);
+        return Rn == Reg::R18;
     }
 
-    bool FCVTAS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTAS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTAU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTAU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTPS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTPS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTPU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTPU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTMS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTMS_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTMU_float(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTZS_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FCVTZU_float_int(bool sf, Imm<2> type, Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 
-    bool FJCVTZS(Vec Vn, Reg Rd) {
-        ChooseScratch(Reg::X18, Rd);
-        return false || Rd == Reg::X18;
+    bool FJCVTZS(Vec Vn, Reg Rd) override {
+        ChooseScratch(Reg::R18, Rd);
+        return Rd == Reg::R18;
     }
 };