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@ -1750,38 +1750,31 @@ void RasterizerVulkan::UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs) |
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boost::container::static_vector<VkVertexInputBindingDescription2EXT, 32> bindings; |
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boost::container::static_vector<VkVertexInputAttributeDescription2EXT, 32> attributes; |
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// There seems to be a bug on Nvidia's driver where updating only higher attributes ends up
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// generating dirty state. Track the highest dirty attribute and update all attributes until
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// that one.
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size_t highest_dirty_attr{}; |
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for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) { |
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if (dirty[Dirty::VertexAttribute0 + index]) { |
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highest_dirty_attr = index; |
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} |
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} |
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for (size_t index = 0; index < highest_dirty_attr; ++index) { |
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const u32 max_attributes = |
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static_cast<u32>(std::min<size_t>(Maxwell::NumVertexAttributes, |
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device.GetMaxVertexInputAttributes())); |
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const u32 max_bindings = |
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static_cast<u32>(std::min<size_t>(Maxwell::NumVertexArrays, |
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device.GetMaxVertexInputBindings())); |
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for (u32 index = 0; index < max_attributes; ++index) { |
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const Maxwell::VertexAttribute attribute{regs.vertex_attrib_format[index]}; |
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const u32 binding{attribute.buffer}; |
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dirty[Dirty::VertexAttribute0 + index] = false; |
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dirty[Dirty::VertexBinding0 + static_cast<size_t>(binding)] = true; |
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if (!attribute.constant) { |
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attributes.push_back({ |
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.sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_ATTRIBUTE_DESCRIPTION_2_EXT, |
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.pNext = nullptr, |
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.location = static_cast<u32>(index), |
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.binding = binding, |
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.format = MaxwellToVK::VertexFormat(device, attribute.type, attribute.size), |
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.offset = attribute.offset, |
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}); |
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} |
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} |
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for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) { |
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if (!dirty[Dirty::VertexBinding0 + index]) { |
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if (attribute.constant || binding >= max_bindings) { |
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continue; |
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} |
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dirty[Dirty::VertexBinding0 + index] = false; |
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attributes.push_back({ |
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.sType = VK_STRUCTURE_TYPE_VERTEX_INPUT_ATTRIBUTE_DESCRIPTION_2_EXT, |
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.pNext = nullptr, |
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.location = index, |
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.binding = binding, |
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.format = MaxwellToVK::VertexFormat(device, attribute.type, attribute.size), |
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.offset = attribute.offset, |
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}); |
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} |
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const u32 binding{static_cast<u32>(index)}; |
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for (u32 binding = 0; binding < max_bindings; ++binding) { |
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const auto& input_binding{regs.vertex_streams[binding]}; |
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const bool is_instanced{regs.vertex_stream_instances.IsInstancingEnabled(binding)}; |
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bindings.push_back({ |
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@ -1793,6 +1786,14 @@ void RasterizerVulkan::UpdateVertexInput(Tegra::Engines::Maxwell3D::Regs& regs) |
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.divisor = is_instanced ? input_binding.frequency : 1, |
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}); |
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} |
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for (size_t index = 0; index < Maxwell::NumVertexAttributes; ++index) { |
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dirty[Dirty::VertexAttribute0 + index] = false; |
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} |
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for (size_t index = 0; index < Maxwell::NumVertexArrays; ++index) { |
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dirty[Dirty::VertexBinding0 + index] = false; |
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} |
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scheduler.Record([bindings, attributes](vk::CommandBuffer cmdbuf) { |
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cmdbuf.SetVertexInputEXT(bindings, attributes); |
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}); |
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