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Shader: Initial implementation of x86_x64 JIT compiler for Pica vertex shaders.
Shader: Initial implementation of x86_x64 JIT compiler for Pica vertex shaders.
- Config: Add an option for selecting to use shader JIT or interpreter. - Qt: Add a menu option for enabling/disabling the shader JIT.nce_cpp
19 changed files with 968 additions and 4 deletions
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2externals/nihstro
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1src/citra/citra.cpp
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1src/citra/config.cpp
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4src/citra/default_ini.h
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2src/citra_qt/config.cpp
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8src/citra_qt/main.cpp
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1src/citra_qt/main.h
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9src/citra_qt/main.ui
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1src/core/settings.h
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10src/video_core/CMakeLists.txt
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3src/video_core/pica.cpp
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42src/video_core/shader/shader.cpp
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3src/video_core/shader/shader.h
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36src/video_core/shader/shader_jit.cpp
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85src/video_core/shader/shader_jit.h
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91src/video_core/shader/shader_jit_fake.cpp
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669src/video_core/shader/shader_jit_x64.cpp
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1src/video_core/video_core.cpp
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3src/video_core/video_core.h
@ -1 +1 @@ |
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Subproject commit 676254f71e0a7ef0aca8acce078d3c3dc80ccf70 |
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Subproject commit 445cba0b2ff8d348368e32698e4760a670260bfc |
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@ -0,0 +1,36 @@ |
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "video_core/pica.h"
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#include "shader.h"
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#include "shader_jit.h"
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namespace Pica { |
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namespace Shader { |
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JitShader::JitShader() : jitted(nullptr) { |
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} |
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void JitShader::DoJit(JitCompiler& jit) { |
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jitted = jit.Compile(); |
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} |
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void JitShader::Run(UnitState& state) { |
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if (jitted) |
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jitted(&state); |
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} |
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JitCompiler::JitCompiler() { |
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AllocCodeSpace(1024 * 1024 * 4); |
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} |
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void JitCompiler::Clear() { |
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ClearCodeSpace(); |
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} |
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} // namespace Shader
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} // namespace Pica
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// Copyright 2015 Citra Emulator Project |
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// Licensed under GPLv2 or any later version |
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// Refer to the license.txt file included. |
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#pragma once |
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#include <nihstro/shader_bytecode.h> |
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#if defined(_M_X86_64) |
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#include "common/x64_emitter.h" |
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#else |
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#include "common/fake_emitter.h" |
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#endif |
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#include "video_core/pica.h" |
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#include "shader.h" |
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using nihstro::Instruction; |
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using nihstro::OpCode; |
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using nihstro::SwizzlePattern; |
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namespace Pica { |
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namespace Shader { |
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using CompiledShader = void(void* state); |
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/** |
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* This class implements the shader JIT compiler. It recompiles a Pica shader program into x86_64 |
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* code that can be executed on the host machine directly. |
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*/ |
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class JitCompiler : public Gen::XCodeBlock { |
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public: |
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JitCompiler(); |
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CompiledShader* Compile(); |
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void Clear(); |
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void Compile_ADD(Instruction instr); |
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void Compile_DP3(Instruction instr); |
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void Compile_DP4(Instruction instr); |
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void Compile_MUL(Instruction instr); |
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void Compile_FLR(Instruction instr); |
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void Compile_MAX(Instruction instr); |
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void Compile_MIN(Instruction instr); |
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void Compile_RCP(Instruction instr); |
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void Compile_RSQ(Instruction instr); |
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void Compile_MOVA(Instruction instr); |
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void Compile_MOV(Instruction instr); |
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void Compile_SLTI(Instruction instr); |
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void Compile_NOP(Instruction instr); |
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void Compile_END(Instruction instr); |
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void Compile_CALL(Instruction instr); |
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void Compile_CALLC(Instruction instr); |
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void Compile_CALLU(Instruction instr); |
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void Compile_IF(Instruction instr); |
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void Compile_LOOP(Instruction instr); |
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void Compile_JMP(Instruction instr); |
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void Compile_CMP(Instruction instr); |
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void Compile_MAD(Instruction instr); |
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private: |
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void Compile_Block(unsigned stop); |
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void Compile_NextInstr(unsigned* offset); |
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#if defined(_M_X86_64) |
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void Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRegister src_reg, Gen::X64Reg dest); |
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void Compile_DestEnable(Instruction instr, Gen::X64Reg dest); |
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void Compile_EvaluateCondition(Instruction instr); |
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void Compile_UniformCondition(Instruction instr); |
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#endif |
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/// Pointer to the variable that stores the current Pica code offset. Used to handle nested code blocks. |
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unsigned* offset_ptr = nullptr; |
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bool done = false; |
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bool looping = false; |
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}; |
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} // Shader |
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} // Pica |
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@ -0,0 +1,91 @@ |
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/fake_emitter.h"
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#include "video_core/shader/shader.h"
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#include "video_core/shader/shader_jit.h"
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namespace Pica { |
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namespace Shader { |
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using namespace FakeGen; |
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void Jit::Comp_ADD(Instruction instr) { |
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} |
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void Jit::Comp_DP3(Instruction instr) { |
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} |
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void Jit::Comp_DP4(Instruction instr) { |
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} |
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void Jit::Comp_MUL(Instruction instr) { |
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} |
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void Jit::Comp_FLR(Instruction instr) { |
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} |
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void Jit::Comp_MAX(Instruction instr) { |
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} |
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void Jit::Comp_MIN(Instruction instr) { |
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} |
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void Jit::Comp_MOVA(Instruction instr) { |
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} |
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void Jit::Comp_MOV(Instruction instr) { |
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} |
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void Jit::Comp_SLTI(Instruction instr) { |
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} |
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void Jit::Comp_RCP(Instruction instr) { |
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} |
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void Jit::Comp_RSQ(Instruction instr) { |
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} |
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void Jit::Comp_NOP(Instruction instr) { |
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} |
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void Jit::Comp_END(Instruction instr) { |
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} |
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void Jit::Comp_CALL(Instruction instr) { |
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} |
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void Jit::Comp_CALLC(Instruction instr) { |
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} |
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void Jit::Comp_CALLU(Instruction instr) { |
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} |
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void Jit::Comp_CMP(Instruction instr) { |
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} |
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void Jit::Comp_MAD(Instruction instr) { |
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} |
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void Jit::Comp_IF(Instruction instr) { |
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} |
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void Jit::Comp_LOOP(Instruction instr) { |
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} |
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void Jit::Comp_JMP(Instruction instr) { |
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} |
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void Jit::Comp_NextInstr(unsigned* offset) { |
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} |
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CompiledShader Jit::Compile() { |
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return nullptr; |
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} |
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} // namespace Shader
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} // namespace Pica
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@ -0,0 +1,669 @@ |
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <smmintrin.h>
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#include "common/abi.h"
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#include "common/cpu_detect.h"
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#include "common/x64_emitter.h"
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#include "shader.h"
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#include "shader_jit.h"
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namespace Pica { |
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namespace Shader { |
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using namespace Gen; |
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typedef void (JitCompiler::*JitFunction)(Instruction instr); |
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const JitFunction instr_table[64] = { |
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&JitCompiler::Compile_ADD, // add
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&JitCompiler::Compile_DP3, // dp3
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&JitCompiler::Compile_DP4, // dp4
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nullptr, // dph
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nullptr, // unknown
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nullptr, // ex2
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nullptr, // lg2
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nullptr, // unknown
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&JitCompiler::Compile_MUL, // mul
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nullptr, // lge
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nullptr, // slt
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&JitCompiler::Compile_FLR, // flr
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&JitCompiler::Compile_MAX, // max
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&JitCompiler::Compile_MIN, // min
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&JitCompiler::Compile_RCP, // rcp
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&JitCompiler::Compile_RSQ, // rsq
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nullptr, // unknown
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nullptr, // unknown
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&JitCompiler::Compile_MOVA, // mova
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&JitCompiler::Compile_MOV, // mov
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // dphi
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nullptr, // unknown
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nullptr, // sgei
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&JitCompiler::Compile_SLTI, // slti
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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nullptr, // unknown
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&JitCompiler::Compile_NOP, // nop
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&JitCompiler::Compile_END, // end
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nullptr, // break
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&JitCompiler::Compile_CALL, // call
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&JitCompiler::Compile_CALLC, // callc
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&JitCompiler::Compile_CALLU, // callu
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&JitCompiler::Compile_IF, // ifu
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&JitCompiler::Compile_IF, // ifc
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&JitCompiler::Compile_LOOP, // loop
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nullptr, // emit
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nullptr, // sete
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&JitCompiler::Compile_JMP, // jmpc
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&JitCompiler::Compile_JMP, // jmpu
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&JitCompiler::Compile_CMP, // cmp
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&JitCompiler::Compile_CMP, // cmp
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // madi
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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&JitCompiler::Compile_MAD, // mad
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}; |
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// The following is used to alias some commonly used registers. Generally, RAX-RDX and XMM0-XMM3 can
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// be used as scratch registers within a compiler function. The other registers have designated
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// purposes, as documented below:
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/// Pointer to the uniform memory
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static const X64Reg UNIFORMS = R10; |
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/// The two 32-bit VS address offset registers set by the MOVA instruction
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static const X64Reg ADDROFFS_REG = R11; |
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/// VS loop count register
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static const X64Reg LOOPCOUNT_REG = R12; |
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/// Current VS loop iteration number (we could probably use LOOPCOUNT_REG, but this quicker)
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static const X64Reg LOOPCOUNT = RSI; |
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/// Number to increment LOOPCOUNT_REG by on each loop iteration
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static const X64Reg LOOPINC = RDI; |
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/// Result of the previous CMP instruction for the X-component comparison
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static const X64Reg COND0 = R13; |
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/// Result of the previous CMP instruction for the Y-component comparison
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static const X64Reg COND1 = R14; |
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/// Pointer to the UnitState instance for the current VS unit
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static const X64Reg STATE = R15; |
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/// SIMD scratch register
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static const X64Reg SCRATCH = XMM0; |
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/// Loaded with the first swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC1 = XMM1; |
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/// Loaded with the second swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC2 = XMM2; |
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/// Loaded with the third swizzled source register, otherwise can be used as a scratch register
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static const X64Reg SRC3 = XMM3; |
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/// Constant vector of [1.0f, 1.0f, 1.0f, 1.0f], used to efficiently set a vector to one
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static const X64Reg ONE = XMM14; |
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/// Constant vector of [-0.f, -0.f, -0.f, -0.f], used to efficiently negate a vector with XOR
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static const X64Reg NEGBIT = XMM15; |
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/// Raw constant for the source register selector that indicates no swizzling is performed
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static const u8 NO_SRC_REG_SWIZZLE = 0x1b; |
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/// Raw constant for the destination register enable mask that indicates all components are enabled
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static const u8 NO_DEST_REG_MASK = 0xf; |
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/**
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* Loads and swizzles a source register into the specified XMM register. |
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* @param instr VS instruction, used for determining how to load the source register |
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* @param src_num Number indicating which source register to load (1 = src1, 2 = src2, 3 = src3) |
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* @param src_reg SourceRegister object corresponding to the source register to load |
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* @param dest Destination XMM register to store the loaded, swizzled source register |
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*/ |
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void JitCompiler::Compile_SwizzleSrc(Instruction instr, unsigned src_num, SourceRegister src_reg, X64Reg dest) { |
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X64Reg src_ptr; |
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std::size_t src_offset; |
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if (src_reg.GetRegisterType() == RegisterType::FloatUniform) { |
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src_ptr = UNIFORMS; |
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src_offset = src_reg.GetIndex() * sizeof(float24) * 4; |
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} else { |
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src_ptr = STATE; |
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src_offset = UnitState::InputOffset(src_reg); |
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} |
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unsigned operand_desc_id; |
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD || |
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instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) { |
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// The MAD and MADI instructions do not use the address offset registers, so loading the
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// source is a bit simpler here
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operand_desc_id = instr.mad.operand_desc_id; |
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// Load the source
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MOVAPS(dest, MDisp(src_ptr, src_offset)); |
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} else { |
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operand_desc_id = instr.common.operand_desc_id; |
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const bool is_inverted = (0 != (instr.opcode.Value().GetInfo().subtype & OpCode::Info::SrcInversed)); |
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unsigned offset_src = is_inverted ? 2 : 1; |
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if (src_num == offset_src && instr.common.address_register_index != 0) { |
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switch (instr.common.address_register_index) { |
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case 1: // address offset 1
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MOV(32, R(RBX), R(ADDROFFS_REG)); |
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break; |
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case 2: // address offset 2
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MOV(64, R(RBX), R(ADDROFFS_REG)); |
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SHR(64, R(RBX), Imm8(32)); |
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break; |
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case 3: // adddress offet 3
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MOV(64, R(RBX), R(LOOPCOUNT_REG)); |
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break; |
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default: |
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UNREACHABLE(); |
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break; |
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} |
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MOVAPS(dest, MComplex(src_ptr, RBX, 1, src_offset)); |
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} else { |
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// Load the source
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MOVAPS(dest, MDisp(src_ptr, src_offset)); |
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} |
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} |
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SwizzlePattern swiz = { g_state.vs.swizzle_data[operand_desc_id] }; |
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// Generate instructions for source register swizzling as needed
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u8 sel = swiz.GetRawSelector(src_num); |
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if (sel != NO_SRC_REG_SWIZZLE) { |
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// Selector component order needs to be reversed for the SHUFPS instruction
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sel = ((sel & 0xc0) >> 6) | ((sel & 3) << 6) | ((sel & 0xc) << 2) | ((sel & 0x30) >> 2); |
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// Shuffle inputs for swizzle
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SHUFPS(dest, R(dest), sel); |
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} |
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// If the source register should be negated, flip the negative bit using XOR
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const bool negate[] = { swiz.negate_src1, swiz.negate_src2, swiz.negate_src3 }; |
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if (negate[src_num - 1]) { |
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XORPS(dest, R(NEGBIT)); |
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} |
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} |
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void JitCompiler::Compile_DestEnable(Instruction instr,X64Reg src) { |
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DestRegister dest; |
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unsigned operand_desc_id; |
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if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MAD || |
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instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) { |
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operand_desc_id = instr.mad.operand_desc_id; |
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dest = instr.mad.dest.Value(); |
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} else { |
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operand_desc_id = instr.common.operand_desc_id; |
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dest = instr.common.dest.Value(); |
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} |
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SwizzlePattern swiz = { g_state.vs.swizzle_data[operand_desc_id] }; |
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// If all components are enabled, write the result to the destination register
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if (swiz.dest_mask == NO_DEST_REG_MASK) { |
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// Store dest back to memory
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MOVAPS(MDisp(STATE, UnitState::OutputOffset(dest)), src); |
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} else { |
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// Not all components are enabled, so mask the result when storing to the destination register...
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MOVAPS(SCRATCH, MDisp(STATE, UnitState::OutputOffset(dest))); |
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if (Common::cpu_info.bSSE4_1) { |
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u8 mask = ((swiz.dest_mask & 1) << 3) | ((swiz.dest_mask & 8) >> 3) | ((swiz.dest_mask & 2) << 1) | ((swiz.dest_mask & 4) >> 1); |
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BLENDPS(SCRATCH, R(src), mask); |
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} else { |
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MOVAPS(XMM4, R(src)); |
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UNPCKHPS(XMM4, R(SCRATCH)); // Unpack X/Y components of source and destination
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UNPCKLPS(SCRATCH, R(src)); // Unpack Z/W components of source and destination
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// Compute selector to selectively copy source components to destination for SHUFPS instruction
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u8 sel = ((swiz.DestComponentEnabled(0) ? 1 : 0) << 0) | |
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((swiz.DestComponentEnabled(1) ? 3 : 2) << 2) | |
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((swiz.DestComponentEnabled(2) ? 0 : 1) << 4) | |
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((swiz.DestComponentEnabled(3) ? 2 : 3) << 6); |
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SHUFPS(SCRATCH, R(XMM4), sel); |
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} |
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// Store dest back to memory
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MOVAPS(MDisp(STATE, UnitState::OutputOffset(dest)), SCRATCH); |
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} |
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} |
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void JitCompiler::Compile_EvaluateCondition(Instruction instr) { |
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// Note: NXOR is used below to check for equality
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switch (instr.flow_control.op) { |
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case Instruction::FlowControlType::Or: |
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MOV(32, R(RAX), R(COND0)); |
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MOV(32, R(RBX), R(COND1)); |
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XOR(32, R(RAX), Imm32(instr.flow_control.refx.Value() ^ 1)); |
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XOR(32, R(RBX), Imm32(instr.flow_control.refy.Value() ^ 1)); |
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OR(32, R(RAX), R(RBX)); |
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break; |
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|
|||
case Instruction::FlowControlType::And: |
|||
MOV(32, R(RAX), R(COND0)); |
|||
MOV(32, R(RBX), R(COND1)); |
|||
XOR(32, R(RAX), Imm32(instr.flow_control.refx.Value() ^ 1)); |
|||
XOR(32, R(RBX), Imm32(instr.flow_control.refy.Value() ^ 1)); |
|||
AND(32, R(RAX), R(RBX)); |
|||
break; |
|||
|
|||
case Instruction::FlowControlType::JustX: |
|||
MOV(32, R(RAX), R(COND0)); |
|||
XOR(32, R(RAX), Imm32(instr.flow_control.refx.Value() ^ 1)); |
|||
break; |
|||
|
|||
case Instruction::FlowControlType::JustY: |
|||
MOV(32, R(RAX), R(COND1)); |
|||
XOR(32, R(RAX), Imm32(instr.flow_control.refy.Value() ^ 1)); |
|||
break; |
|||
} |
|||
} |
|||
|
|||
void JitCompiler::Compile_UniformCondition(Instruction instr) { |
|||
int offset = offsetof(decltype(g_state.vs.uniforms), b) + (instr.flow_control.bool_uniform_id * sizeof(bool)); |
|||
CMP(sizeof(bool) * 8, MDisp(UNIFORMS, offset), Imm8(0)); |
|||
} |
|||
|
|||
void JitCompiler::Compile_ADD(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
ADDPS(SRC1, R(SRC2)); |
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_DP3(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
|
|||
if (Common::cpu_info.bSSE4_1) { |
|||
DPPS(SRC1, R(SRC2), 0x7f); |
|||
} else { |
|||
MULPS(SRC1, R(SRC2)); |
|||
|
|||
MOVAPS(SRC2, R(SRC1)); |
|||
SHUFPS(SRC2, R(SRC2), _MM_SHUFFLE(1, 1, 1, 1)); |
|||
|
|||
MOVAPS(SRC3, R(SRC1)); |
|||
SHUFPS(SRC3, R(SRC3), _MM_SHUFFLE(2, 2, 2, 2)); |
|||
|
|||
SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 0, 0, 0)); |
|||
ADDPS(SRC1, R(SRC2)); |
|||
ADDPS(SRC1, R(SRC3)); |
|||
} |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_DP4(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
|
|||
if (Common::cpu_info.bSSE4_1) { |
|||
DPPS(SRC1, R(SRC2), 0xff); |
|||
} else { |
|||
MULPS(SRC1, R(SRC2)); |
|||
|
|||
MOVAPS(SRC2, R(SRC1)); |
|||
SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(2, 3, 0, 1)); // XYZW -> ZWXY
|
|||
ADDPS(SRC1, R(SRC2)); |
|||
|
|||
MOVAPS(SRC2, R(SRC1)); |
|||
SHUFPS(SRC1, R(SRC1), _MM_SHUFFLE(0, 1, 2, 3)); // XYZW -> WZYX
|
|||
ADDPS(SRC1, R(SRC2)); |
|||
} |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_MUL(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
MULPS(SRC1, R(SRC2)); |
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_FLR(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
|
|||
if (Common::cpu_info.bSSE4_1) { |
|||
ROUNDFLOORPS(SRC1, R(SRC1)); |
|||
} else { |
|||
CVTPS2DQ(SRC1, R(SRC1)); |
|||
CVTDQ2PS(SRC1, R(SRC1)); |
|||
} |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_MAX(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
MAXPS(SRC1, R(SRC2)); |
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_MIN(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
MINPS(SRC1, R(SRC2)); |
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_MOVA(Instruction instr) { |
|||
SwizzlePattern swiz = { g_state.vs.swizzle_data[instr.common.operand_desc_id] }; |
|||
|
|||
if (!swiz.DestComponentEnabled(0) && !swiz.DestComponentEnabled(1)) { |
|||
return; // NoOp
|
|||
} |
|||
|
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
|
|||
// Convert floats to integers (only care about X and Y components)
|
|||
CVTPS2DQ(SRC1, R(SRC1)); |
|||
|
|||
// Get result
|
|||
MOVQ_xmm(R(RAX), SRC1); |
|||
SHL(64, R(RAX), Imm8(4)); // Multiply by 16 to be used as an offset later
|
|||
|
|||
// Handle destination enable
|
|||
if (swiz.DestComponentEnabled(0) && swiz.DestComponentEnabled(1)) { |
|||
MOV(64, R(ADDROFFS_REG), R(RAX)); // Overwrite both
|
|||
} else { |
|||
if (swiz.DestComponentEnabled(0)) { |
|||
// Preserve Y-component
|
|||
|
|||
// Clear low 32 bits of previous address register
|
|||
MOV(32, R(RBX), R(ADDROFFS_REG)); |
|||
XOR(64, R(ADDROFFS_REG), R(RBX)); |
|||
|
|||
// Clear high 32-bits of new address register
|
|||
MOV(32, R(RAX), R(RAX)); |
|||
} else if (swiz.DestComponentEnabled(1)) { |
|||
// Preserve X-component
|
|||
|
|||
// Clear high 32-bits of previous address register
|
|||
MOV(32, R(ADDROFFS_REG), R(ADDROFFS_REG)); |
|||
|
|||
// Clear low 32 bits of new address register
|
|||
MOV(32, R(RBX), R(RAX)); |
|||
XOR(64, R(RAX), R(RBX)); |
|||
} |
|||
|
|||
OR(64, R(ADDROFFS_REG), R(RAX)); // Combine result
|
|||
} |
|||
} |
|||
|
|||
void JitCompiler::Compile_MOV(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_SLTI(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1i, SRC1); |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src2i, SRC2); |
|||
|
|||
CMPSS(SRC1, R(SRC2), CMP_LT); |
|||
ANDPS(SRC1, R(ONE)); |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_RCP(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
|
|||
// TODO(bunnei): RCPPS is a pretty rough approximation, this might cause problems if Pica
|
|||
// performs this operation more accurately. This should be checked on hardware.
|
|||
RCPPS(SRC1, R(SRC1)); |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_RSQ(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
|
|||
// TODO(bunnei): RSQRTPS is a pretty rough approximation, this might cause problems if Pica
|
|||
// performs this operation more accurately. This should be checked on hardware.
|
|||
RSQRTPS(SRC1, R(SRC1)); |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_NOP(Instruction instr) { |
|||
} |
|||
|
|||
void JitCompiler::Compile_END(Instruction instr) { |
|||
ABI_PopAllCalleeSavedRegsAndAdjustStack(); |
|||
RET(); |
|||
done = true; |
|||
} |
|||
|
|||
void JitCompiler::Compile_CALL(Instruction instr) { |
|||
unsigned offset = instr.flow_control.dest_offset; |
|||
while (offset < (instr.flow_control.dest_offset + instr.flow_control.num_instructions)) { |
|||
Compile_NextInstr(&offset); |
|||
} |
|||
} |
|||
|
|||
void JitCompiler::Compile_CALLC(Instruction instr) { |
|||
Compile_EvaluateCondition(instr); |
|||
FixupBranch b = J_CC(CC_Z, true); |
|||
Compile_CALL(instr); |
|||
SetJumpTarget(b); |
|||
} |
|||
|
|||
void JitCompiler::Compile_CALLU(Instruction instr) { |
|||
Compile_UniformCondition(instr); |
|||
FixupBranch b = J_CC(CC_Z, true); |
|||
Compile_CALL(instr); |
|||
SetJumpTarget(b); |
|||
} |
|||
|
|||
void JitCompiler::Compile_CMP(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.common.src1, SRC1); |
|||
Compile_SwizzleSrc(instr, 2, instr.common.src2, SRC2); |
|||
|
|||
static const u8 cmp[] = { CMP_EQ, CMP_NEQ, CMP_LT, CMP_LE, CMP_NLE, CMP_NLT }; |
|||
|
|||
if (instr.common.compare_op.x == instr.common.compare_op.y) { |
|||
// Compare X-component and Y-component together
|
|||
CMPPS(SRC1, R(SRC2), cmp[instr.common.compare_op.x]); |
|||
|
|||
MOVQ_xmm(R(COND0), SRC1); |
|||
MOV(64, R(COND1), R(COND0)); |
|||
} else { |
|||
// Compare X-component
|
|||
MOVAPS(SCRATCH, R(SRC1)); |
|||
CMPSS(SCRATCH, R(SRC2), cmp[instr.common.compare_op.x]); |
|||
|
|||
// Compare Y-component
|
|||
CMPPS(SRC1, R(SRC2), cmp[instr.common.compare_op.y]); |
|||
|
|||
MOVQ_xmm(R(COND0), SCRATCH); |
|||
MOVQ_xmm(R(COND1), SRC1); |
|||
} |
|||
|
|||
SHR(32, R(COND0), Imm8(31)); |
|||
SHR(64, R(COND1), Imm8(63)); |
|||
} |
|||
|
|||
void JitCompiler::Compile_MAD(Instruction instr) { |
|||
Compile_SwizzleSrc(instr, 1, instr.mad.src1, SRC1); |
|||
|
|||
if (instr.opcode.Value().EffectiveOpCode() == OpCode::Id::MADI) { |
|||
Compile_SwizzleSrc(instr, 2, instr.mad.src2i, SRC2); |
|||
Compile_SwizzleSrc(instr, 3, instr.mad.src3i, SRC3); |
|||
} else { |
|||
Compile_SwizzleSrc(instr, 2, instr.mad.src2, SRC2); |
|||
Compile_SwizzleSrc(instr, 3, instr.mad.src3, SRC3); |
|||
} |
|||
|
|||
if (Common::cpu_info.bFMA) { |
|||
VFMADD213PS(SRC1, SRC2, R(SRC3)); |
|||
} else { |
|||
MULPS(SRC1, R(SRC2)); |
|||
ADDPS(SRC1, R(SRC3)); |
|||
} |
|||
|
|||
Compile_DestEnable(instr, SRC1); |
|||
} |
|||
|
|||
void JitCompiler::Compile_IF(Instruction instr) { |
|||
ASSERT_MSG(instr.flow_control.dest_offset > *offset_ptr, "Backwards if-statements not supported"); |
|||
|
|||
// Evaluate the "IF" condition
|
|||
if (instr.opcode.Value() == OpCode::Id::IFU) { |
|||
Compile_UniformCondition(instr); |
|||
} else if (instr.opcode.Value() == OpCode::Id::IFC) { |
|||
Compile_EvaluateCondition(instr); |
|||
} |
|||
FixupBranch b = J_CC(CC_Z, true); |
|||
|
|||
// Compile the code that corresponds to the condition evaluating as true
|
|||
Compile_Block(instr.flow_control.dest_offset - 1); |
|||
|
|||
// If there isn't an "ELSE" condition, we are done here
|
|||
if (instr.flow_control.num_instructions == 0) { |
|||
SetJumpTarget(b); |
|||
return; |
|||
} |
|||
|
|||
FixupBranch b2 = J(true); |
|||
|
|||
SetJumpTarget(b); |
|||
|
|||
// This code corresponds to the "ELSE" condition
|
|||
// Comple the code that corresponds to the condition evaluating as false
|
|||
Compile_Block(instr.flow_control.dest_offset + instr.flow_control.num_instructions - 1); |
|||
|
|||
SetJumpTarget(b2); |
|||
} |
|||
|
|||
void JitCompiler::Compile_LOOP(Instruction instr) { |
|||
ASSERT_MSG(instr.flow_control.dest_offset > *offset_ptr, "Backwards loops not supported"); |
|||
ASSERT_MSG(!looping, "Nested loops not supported"); |
|||
|
|||
looping = true; |
|||
|
|||
int offset = offsetof(decltype(g_state.vs.uniforms), i) + (instr.flow_control.int_uniform_id * sizeof(Math::Vec4<u8>)); |
|||
MOV(32, R(LOOPCOUNT), MDisp(UNIFORMS, offset)); |
|||
MOV(32, R(LOOPCOUNT_REG), R(LOOPCOUNT)); |
|||
SHR(32, R(LOOPCOUNT_REG), Imm8(8)); |
|||
AND(32, R(LOOPCOUNT_REG), Imm32(0xff)); // Y-component is the start
|
|||
MOV(32, R(LOOPINC), R(LOOPCOUNT)); |
|||
SHR(32, R(LOOPINC), Imm8(16)); |
|||
MOVZX(32, 8, LOOPINC, R(LOOPINC)); // Z-component is the incrementer
|
|||
MOVZX(32, 8, LOOPCOUNT, R(LOOPCOUNT)); // X-component is iteration count
|
|||
ADD(32, R(LOOPCOUNT), Imm8(1)); // Iteration count is X-component + 1
|
|||
|
|||
auto loop_start = GetCodePtr(); |
|||
|
|||
Compile_Block(instr.flow_control.dest_offset); |
|||
|
|||
ADD(32, R(LOOPCOUNT_REG), R(LOOPINC)); // Increment LOOPCOUNT_REG by Z-component
|
|||
SUB(32, R(LOOPCOUNT), Imm8(1)); // Increment loop count by 1
|
|||
J_CC(CC_NZ, loop_start); // Loop if not equal
|
|||
|
|||
looping = false; |
|||
} |
|||
|
|||
void JitCompiler::Compile_JMP(Instruction instr) { |
|||
ASSERT_MSG(instr.flow_control.dest_offset > *offset_ptr, "Backwards jumps not supported"); |
|||
|
|||
if (instr.opcode.Value() == OpCode::Id::JMPC) |
|||
Compile_EvaluateCondition(instr); |
|||
else if (instr.opcode.Value() == OpCode::Id::JMPU) |
|||
Compile_UniformCondition(instr); |
|||
else |
|||
UNREACHABLE(); |
|||
|
|||
FixupBranch b = J_CC(CC_NZ, true); |
|||
|
|||
Compile_Block(instr.flow_control.dest_offset); |
|||
|
|||
SetJumpTarget(b); |
|||
} |
|||
|
|||
void JitCompiler::Compile_Block(unsigned stop) { |
|||
// Save current offset pointer
|
|||
unsigned* prev_offset_ptr = offset_ptr; |
|||
unsigned offset = *prev_offset_ptr; |
|||
|
|||
while (offset <= stop) |
|||
Compile_NextInstr(&offset); |
|||
|
|||
// Restore current offset pointer
|
|||
offset_ptr = prev_offset_ptr; |
|||
*offset_ptr = offset; |
|||
} |
|||
|
|||
void JitCompiler::Compile_NextInstr(unsigned* offset) { |
|||
offset_ptr = offset; |
|||
|
|||
Instruction instr = *(Instruction*)&g_state.vs.program_code[(*offset_ptr)++]; |
|||
OpCode::Id opcode = instr.opcode.Value(); |
|||
auto instr_func = instr_table[static_cast<unsigned>(opcode)]; |
|||
|
|||
if (instr_func) { |
|||
// JIT the instruction!
|
|||
((*this).*instr_func)(instr); |
|||
} else { |
|||
// Unhandled instruction
|
|||
LOG_CRITICAL(HW_GPU, "Unhandled instruction: 0x%02x (0x%08x)", instr.opcode.Value(), instr.hex); |
|||
} |
|||
} |
|||
|
|||
CompiledShader* JitCompiler::Compile() { |
|||
const u8* start = GetCodePtr(); |
|||
const auto& code = g_state.vs.program_code; |
|||
unsigned offset = g_state.regs.vs.main_offset; |
|||
|
|||
ABI_PushAllCalleeSavedRegsAndAdjustStack(); |
|||
|
|||
MOV(PTRBITS, R(STATE), R(ABI_PARAM1)); |
|||
MOV(PTRBITS, R(UNIFORMS), ImmPtr(&g_state.vs.uniforms)); |
|||
|
|||
// Zero address/loop registers
|
|||
XOR(64, R(ADDROFFS_REG_0), R(ADDROFFS_REG_0)); |
|||
XOR(64, R(ADDROFFS_REG_1), R(ADDROFFS_REG_1)); |
|||
XOR(64, R(LOOPCOUNT_REG), R(LOOPCOUNT_REG)); |
|||
|
|||
// Used to set a register to one
|
|||
static const __m128 one = { 1.f, 1.f, 1.f, 1.f }; |
|||
MOV(PTRBITS, R(RAX), ImmPtr(&one)); |
|||
MOVAPS(ONE, MDisp(RAX, 0)); |
|||
|
|||
// Used to negate registers
|
|||
static const __m128 neg = { -0.f, -0.f, -0.f, -0.f }; |
|||
MOV(PTRBITS, R(RAX), ImmPtr(&neg)); |
|||
MOVAPS(NEGBIT, MDisp(RAX, 0)); |
|||
|
|||
looping = false; |
|||
done = false; |
|||
while (offset < g_state.vs.program_code.size()) { |
|||
Compile_NextInstr(&offset); |
|||
} |
|||
|
|||
return (CompiledShader*)start; |
|||
} |
|||
|
|||
} // namespace Shader
|
|||
|
|||
} // namespace Pica
|
|||
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