[vk] Fixes regression of PR #180 vk_scheduler.cpp for AMD GPU and Windows OS (#3071)

Fixes AMD + Windows because it forces barriers to include the fragment test and color output stages explicitly, ensuring that all render pass writes are visible before later commands. Without it, AMD’s driver sometimes skipped synchronization, causing broken rendering in Final Fantasy Tactics.

PR #3069 also fixes this regression by reverting vk_scheduler.cpp in PR #180.
This PR fixes PR #180 and may be the better solution.

Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3071
Reviewed-by: crueter <crueter@eden-emu.dev>
Reviewed-by: Lizzie <lizzie@eden-emu.dev>
Co-authored-by: John <john@eden-emu.dev>
Co-committed-by: John <john@eden-emu.dev>

src/video_core/renderer_vulkan/vk_scheduler.cpp

@@ -287,10 +287,10 @@ void Scheduler::EndRenderPass()
 
             for (size_t i = 0; i < num_images; ++i) {
                 const VkImageSubresourceRange& range = ranges[i];
-                const bool is_color = range.aspectMask & VK_IMAGE_ASPECT_COLOR_BIT;
-                const bool is_depth_stencil = range.aspectMask
+                const bool is_color = (range.aspectMask & VK_IMAGE_ASPECT_COLOR_BIT) != 0;
+                const bool is_depth_stencil = (range.aspectMask
                                               & (VK_IMAGE_ASPECT_DEPTH_BIT
-                                                 | VK_IMAGE_ASPECT_STENCIL_BIT);
+                                                 | VK_IMAGE_ASPECT_STENCIL_BIT)) !=0;
 
                 VkAccessFlags src_access = 0;
                 VkPipelineStageFlags this_stage = 0;
@@ -326,14 +326,19 @@ void Scheduler::EndRenderPass()
                 };
             }
 
+            // Graft: ensure explicit fragment tests + color output stages are always synchronized (AMD/Windows fix)
+            src_stages |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
+                    VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
+                    VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
+
             cmdbuf.EndRenderPass();
 
             cmdbuf.PipelineBarrier(src_stages,
                                    VK_PIPELINE_STAGE_ALL_COMMANDS_BIT,
                                    0,
-                                   {},
-                                   {},
-                                   {barriers.data(), num_images} // Batched image barriers
+                                   nullptr,
+                                   nullptr,
+                                   vk::Span(barriers.data(), num_images)  // Batched image barriers
             );
         });