From bd7d0e0466d9abf4bd69cddd3964088659bf055c Mon Sep 17 00:00:00 2001
From: lizzie <lizzie@eden-emu.dev>
Date: Thu, 5 Feb 2026 05:09:46 +0100
Subject: [PATCH] [dynarmic] remove RNG from ARM64 regalloc, use incremental
 LRU (#3416)

- Backported from Azahar's dynarmic <https://github.com/azahar-emu/dynarmic/commit/526227eebe1efff3fb14dbf494b9c5b44c2e9c1f>

> From: PabloMK7 <hackyglitch2@gmail.com>
> Date: Sun, 4 Jan 2026 13:57:44 +0100
> Subject: [PATCH] backend: Do not use random generator for reg allocation (#7)

Signed-off-by: lizzie <lizzie@eden-emu.dev>
Reviewed-on: https://git.eden-emu.dev/eden-emu/eden/pulls/3416
Reviewed-by: DraVee <dravee@eden-emu.dev>
Reviewed-by: crueter <crueter@eden-emu.dev>
Co-authored-by: lizzie <lizzie@eden-emu.dev>
Co-committed-by: lizzie <lizzie@eden-emu.dev>
---
 src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp |  7 ++++---
 src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h   | 10 +++++++---
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
index 3bd5ed90e4..e98a2f6e71 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.cpp
@@ -433,9 +433,10 @@ int RegAlloc::AllocateRegister(const std::array<HostLocInfo, 32>& regs, const st
     std::vector<int> candidates;
     std::copy_if(order.begin(), order.end(), std::back_inserter(candidates), [&](int i) { return regs[i].MaybeAllocatable(); });
 
-    // TODO: LRU
-    std::uniform_int_distribution<size_t> dis{0, candidates.size() - 1};
-    return candidates[dis(rand_gen)];
+    // TODO: The candidate was chosen randomly before, and a LRU was
+    // suggested as an improvement. However, using an incrementing index
+    // seems to be close enough. Determine if an LRU is still needed.
+    return candidates[alloc_candidate_index++ % candidates.size()];
 }
 
 void RegAlloc::SpillGpr(int index) {
diff --git a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
index a8395a068d..87446a240b 100644
--- a/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
+++ b/src/dynarmic/src/dynarmic/backend/arm64/reg_alloc.h
@@ -160,8 +160,12 @@ class RegAlloc final {
 public:
     using ArgumentInfo = std::array<Argument, IR::max_arg_count>;
 
-    explicit RegAlloc(oaknut::CodeGenerator& code, FpsrManager& fpsr_manager, std::vector<int> gpr_order, std::vector<int> fpr_order)
-            : code{code}, fpsr_manager{fpsr_manager}, gpr_order{gpr_order}, fpr_order{fpr_order}, rand_gen{std::random_device{}()} {}
+    explicit RegAlloc(oaknut::CodeGenerator& code, FpsrManager& fpsr_manager, std::vector<int> gpr_order, std::vector<int> fpr_order) noexcept
+        : code{code}
+        , fpsr_manager{fpsr_manager}
+        , gpr_order{gpr_order}
+        , fpr_order{fpr_order}
+    {}
 
     ArgumentInfo GetArgumentInfo(IR::Inst* inst);
     bool WasValueDefined(IR::Inst* inst) const;
@@ -331,7 +335,7 @@ private:
     HostLocInfo flags;
     std::array<HostLocInfo, SpillCount> spills;
 
-    mutable std::mt19937 rand_gen;
+    mutable size_t alloc_candidate_index = 0;
     ankerl::unordered_dense::set<const IR::Inst*> defined_insts;
 };