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@ -87,26 +87,33 @@ void EmitIR<IR::Opcode::NZCVFromPackedFlags>(powah::Context&, EmitContext&, IR:: |
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UNREACHABLE(); |
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} |
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EmittedBlockInfo EmitPPC64(powah::Context& as, IR::Block block, const EmitConfig& emit_conf) { |
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EmittedBlockInfo EmitPPC64(powah::Context& code, IR::Block block, const EmitConfig& emit_conf) { |
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EmittedBlockInfo ebi; |
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RegAlloc reg_alloc{as}; |
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RegAlloc reg_alloc{code}; |
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EmitContext ctx{block, reg_alloc, emit_conf, ebi}; |
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//ebi.entry_point = reinterpret_cast<CodePtr>(as.GetCursorPointer());
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ebi.entry_point = CodePtr(code.base + code.offset); |
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code.BLR(); |
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// Non-volatile saves
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std::vector<u32> gpr_order{GPR_ORDER}; |
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for (size_t i = 0; i < gpr_order.size(); ++i) |
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code.STD(powah::GPR{gpr_order[i]}, powah::R1, -(i * 8)); |
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for (auto iter = block.begin(); iter != block.end(); ++iter) { |
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IR::Inst* inst = &*iter; |
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switch (inst->GetOpcode()) { |
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#define OPCODE(name, type, ...) \
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case IR::Opcode::name: \ |
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EmitIR<IR::Opcode::name>(as, ctx, inst); \ |
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EmitIR<IR::Opcode::name>(code, ctx, inst); \ |
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break; |
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#define A32OPC(name, type, ...) \
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case IR::Opcode::A32##name: \ |
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EmitIR<IR::Opcode::A32##name>(as, ctx, inst); \ |
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EmitIR<IR::Opcode::A32##name>(code, ctx, inst); \ |
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break; |
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#define A64OPC(name, type, ...) \
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case IR::Opcode::A64##name: \ |
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EmitIR<IR::Opcode::A64##name>(as, ctx, inst); \ |
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EmitIR<IR::Opcode::A64##name>(code, ctx, inst); \ |
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break; |
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#include "dynarmic/ir/opcodes.inc"
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#undef OPCODE
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@ -116,8 +123,11 @@ EmittedBlockInfo EmitPPC64(powah::Context& as, IR::Block block, const EmitConfig |
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UNREACHABLE(); |
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} |
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} |
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//UNREACHABLE();
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//ebi.size = reinterpret_cast<CodePtr>(as.GetCursorPointer()) - ebi.entry_point;
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for (size_t i = 0; i < gpr_order.size(); ++i) |
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code.LD(powah::GPR{gpr_order[i]}, powah::R1, -(i * 8)); |
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code.BLR(); |
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ebi.size = code.offset; |
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return ebi; |
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} |
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