bunnei
12 years ago
6 changed files with 1098 additions and 251 deletions
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1src/core/CMakeLists.txt
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842src/core/arm/interpreter/armcopro.cpp
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4src/core/arm/interpreter/arminit.cpp
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498src/core/arm/interpreter/mmu/xscale_copro.cpp
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1src/core/core.vcxproj
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3src/core/core.vcxproj.filters
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/* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
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Copyright (C) 1994, 2000 Advanced RISC Machines Ltd. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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#include "core/arm/interpreter/armdefs.h"
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#include "core/arm/interpreter/armos.h"
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#include "core/arm/interpreter/armemu.h"
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#include "core/arm/interpreter/vfp/vfp.h"
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//chy 2005-07-08
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//#include "ansidecl.h"
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//chy -------
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//#include "iwmmxt.h"
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//chy 2005-09-19 add CP6 MRC support (for get irq number and base)
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extern unsigned xscale_cp6_mrc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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//chy 2005-09-19---------------
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extern unsigned xscale_cp13_init (ARMul_State * state); |
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extern unsigned xscale_cp13_exit (ARMul_State * state); |
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extern unsigned xscale_cp13_ldc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword data); |
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extern unsigned xscale_cp13_stc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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extern unsigned xscale_cp13_mrc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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extern unsigned xscale_cp13_mcr (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword data); |
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extern unsigned xscale_cp13_cdp (ARMul_State * state, unsigned type, |
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ARMword instr); |
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extern unsigned xscale_cp13_read_reg (ARMul_State * state, unsigned reg, |
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ARMword * data); |
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extern unsigned xscale_cp13_write_reg (ARMul_State * state, unsigned reg, |
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ARMword data); |
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extern unsigned xscale_cp14_init (ARMul_State * state); |
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extern unsigned xscale_cp14_exit (ARMul_State * state); |
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extern unsigned xscale_cp14_ldc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword data); |
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extern unsigned xscale_cp14_stc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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extern unsigned xscale_cp14_mrc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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extern unsigned xscale_cp14_mcr (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword data); |
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extern unsigned xscale_cp14_cdp (ARMul_State * state, unsigned type, |
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ARMword instr); |
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extern unsigned xscale_cp14_read_reg (ARMul_State * state, unsigned reg, |
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ARMword * data); |
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extern unsigned xscale_cp14_write_reg (ARMul_State * state, unsigned reg, |
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ARMword data); |
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extern unsigned xscale_cp15_init (ARMul_State * state); |
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extern unsigned xscale_cp15_exit (ARMul_State * state); |
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extern unsigned xscale_cp15_ldc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword data); |
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extern unsigned xscale_cp15_stc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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extern unsigned xscale_cp15_mrc (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword * data); |
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extern unsigned xscale_cp15_mcr (ARMul_State * state, unsigned type, |
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ARMword instr, ARMword data); |
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extern unsigned xscale_cp15_cdp (ARMul_State * state, unsigned type, |
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ARMword instr); |
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extern unsigned xscale_cp15_read_reg (ARMul_State * state, unsigned reg, |
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ARMword * data); |
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extern unsigned xscale_cp15_write_reg (ARMul_State * state, unsigned reg, |
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ARMword data); |
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extern unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg, |
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unsigned cpnum); |
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/* Dummy Co-processors. */ |
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static unsigned |
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NoCoPro3R (ARMul_State * state, |
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unsigned a, ARMword b) |
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{ |
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return ARMul_CANT; |
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} |
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static unsigned |
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NoCoPro4R (ARMul_State * state, |
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unsigned a, |
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ARMword b, ARMword c) |
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{ |
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return ARMul_CANT; |
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} |
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static unsigned |
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NoCoPro4W (ARMul_State * state, |
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unsigned a, |
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ARMword b, ARMword * c) |
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{ |
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return ARMul_CANT; |
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} |
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static unsigned |
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NoCoPro5R (ARMul_State * state, |
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unsigned a, |
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ARMword b, |
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ARMword c, ARMword d) |
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{ |
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return ARMul_CANT; |
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} |
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static unsigned |
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NoCoPro5W (ARMul_State * state, |
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unsigned a, |
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ARMword b, |
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ARMword * c, ARMword * d ) |
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{ |
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return ARMul_CANT; |
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} |
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/* The XScale Co-processors. */ |
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/* Coprocessor 15: System Control. */ |
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static void write_cp14_reg (unsigned, ARMword); |
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static ARMword read_cp14_reg (unsigned); |
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/* There are two sets of registers for copro 15.
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One set is available when opcode_2 is 0 and |
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the other set when opcode_2 >= 1. */ |
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static ARMword XScale_cp15_opcode_2_is_0_Regs[16]; |
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static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16]; |
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/* There are also a set of breakpoint registers
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which are accessed via CRm instead of opcode_2. */ |
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static ARMword XScale_cp15_DBR1; |
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static ARMword XScale_cp15_DBCON; |
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static ARMword XScale_cp15_IBCR0; |
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static ARMword XScale_cp15_IBCR1; |
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static unsigned |
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XScale_cp15_init (ARMul_State * state) |
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{ |
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int i; |
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for (i = 16; i--;) { |
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XScale_cp15_opcode_2_is_0_Regs[i] = 0; |
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XScale_cp15_opcode_2_is_not_0_Regs[i] = 0; |
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} |
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/* Initialise the processor ID. */ |
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//chy 2003-03-24, is same as cpu id in skyeye_options.c
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//XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000;
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XScale_cp15_opcode_2_is_0_Regs[0] = 0x69050000; |
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/* Initialise the cache type. */ |
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XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA; |
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/* Initialise the ARM Control Register. */ |
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XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078; |
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return No_exp; |
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} |
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/* Check an access to a register. */ |
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static unsigned |
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check_cp15_access (ARMul_State * state, |
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unsigned reg, |
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unsigned CRm, unsigned opcode_1, unsigned opcode_2) |
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{ |
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/* Do not allow access to these register in USER mode. */ |
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//chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
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if (state->Mode == USER26MODE || state->Mode == USER32MODE ) |
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return ARMul_CANT; |
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/* Opcode_1should be zero. */ |
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if (opcode_1 != 0) |
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return ARMul_CANT; |
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/* Different register have different access requirements. */ |
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switch (reg) { |
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case 0: |
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case 1: |
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/* CRm must be 0. Opcode_2 can be anything. */ |
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if (CRm != 0) |
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return ARMul_CANT; |
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break; |
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case 2: |
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case 3: |
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/* CRm must be 0. Opcode_2 must be zero. */ |
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if ((CRm != 0) || (opcode_2 != 0)) |
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return ARMul_CANT; |
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break; |
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case 4: |
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/* Access not allowed. */ |
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return ARMul_CANT; |
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case 5: |
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case 6: |
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/* Opcode_2 must be zero. CRm must be 0. */ |
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if ((CRm != 0) || (opcode_2 != 0)) |
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return ARMul_CANT; |
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break; |
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case 7: |
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/* Permissable combinations:
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Opcode_2 CRm |
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0 5 |
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0 6 |
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0 7 |
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1 5 |
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1 6 |
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1 10 |
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4 10 |
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5 2 |
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6 5 */ |
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switch (opcode_2) { |
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default: |
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return ARMul_CANT; |
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case 6: |
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if (CRm != 5) |
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return ARMul_CANT; |
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break; |
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case 5: |
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if (CRm != 2) |
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return ARMul_CANT; |
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break; |
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case 4: |
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if (CRm != 10) |
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return ARMul_CANT; |
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break; |
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case 1: |
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if ((CRm != 5) && (CRm != 6) && (CRm != 10)) |
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return ARMul_CANT; |
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break; |
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case 0: |
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if ((CRm < 5) || (CRm > 7)) |
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return ARMul_CANT; |
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break; |
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} |
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break; |
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case 8: |
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/* Permissable combinations:
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Opcode_2 CRm |
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0 5 |
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0 6 |
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0 7 |
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1 5 |
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1 6 */ |
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if (opcode_2 > 1) |
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return ARMul_CANT; |
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if ((CRm < 5) || (CRm > 7)) |
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return ARMul_CANT; |
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if (opcode_2 == 1 && CRm == 7) |
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return ARMul_CANT; |
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break; |
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case 9: |
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/* Opcode_2 must be zero or one. CRm must be 1 or 2. */ |
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if (((CRm != 0) && (CRm != 1)) |
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|| ((opcode_2 != 1) && (opcode_2 != 2))) |
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return ARMul_CANT; |
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break; |
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case 10: |
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/* Opcode_2 must be zero or one. CRm must be 4 or 8. */ |
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if (((CRm != 0) && (CRm != 1)) |
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|| ((opcode_2 != 4) && (opcode_2 != 8))) |
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return ARMul_CANT; |
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break; |
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case 11: |
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/* Access not allowed. */ |
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return ARMul_CANT; |
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case 12: |
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/* Access not allowed. */ |
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return ARMul_CANT; |
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case 13: |
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/* Opcode_2 must be zero. CRm must be 0. */ |
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if ((CRm != 0) || (opcode_2 != 0)) |
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return ARMul_CANT; |
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break; |
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case 14: |
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/* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */ |
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if (opcode_2 != 0) |
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return ARMul_CANT; |
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if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) |
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&& (CRm != 9)) |
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return ARMul_CANT; |
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break; |
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case 15: |
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/* Opcode_2 must be zero. CRm must be 1. */ |
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if ((CRm != 1) || (opcode_2 != 0)) |
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return ARMul_CANT; |
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break; |
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default: |
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/* Should never happen. */ |
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return ARMul_CANT; |
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} |
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return ARMul_DONE; |
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} |
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/* Coprocessor 13: Interrupt Controller and Bus Controller. */ |
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/* There are two sets of registers for copro 13.
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One set (of three registers) is available when CRm is 0 |
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and the other set (of six registers) when CRm is 1. */ |
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static ARMword XScale_cp13_CR0_Regs[16]; |
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static ARMword XScale_cp13_CR1_Regs[16]; |
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static unsigned |
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XScale_cp13_init (ARMul_State * state) |
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{ |
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int i; |
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for (i = 16; i--;) { |
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XScale_cp13_CR0_Regs[i] = 0; |
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XScale_cp13_CR1_Regs[i] = 0; |
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} |
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return No_exp; |
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} |
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/* Check an access to a register. */ |
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static unsigned |
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check_cp13_access (ARMul_State * state, |
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unsigned reg, |
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unsigned CRm, unsigned opcode_1, unsigned opcode_2) |
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{ |
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/* Do not allow access to these registers in USER mode. */ |
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//chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
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if (state->Mode == USER26MODE || state->Mode == USER32MODE ) |
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return ARMul_CANT; |
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/* The opcodes should be zero. */ |
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if ((opcode_1 != 0) || (opcode_2 != 0)) |
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return ARMul_CANT; |
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/* Do not allow access to these register if bit
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13 of coprocessor 15's register 15 is zero. */ |
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if (!CP_ACCESS_ALLOWED (state, 13)) |
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return ARMul_CANT; |
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/* Registers 0, 4 and 8 are defined when CRm == 0.
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Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1. |
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For all other CRm values undefined behaviour results. */ |
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if (CRm == 0) { |
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if (reg == 0 || reg == 4 || reg == 8) |
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return ARMul_DONE; |
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} |
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else if (CRm == 1) { |
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if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8)) |
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return ARMul_DONE; |
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} |
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return ARMul_CANT; |
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} |
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/* Coprocessor 14: Performance Monitoring, Clock and Power management,
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Software Debug. */ |
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static ARMword XScale_cp14_Regs[16]; |
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static unsigned |
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XScale_cp14_init (ARMul_State * state) |
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{ |
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int i; |
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for (i = 16; i--;) |
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XScale_cp14_Regs[i] = 0; |
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return No_exp; |
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} |
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/* Check an access to a register. */ |
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static unsigned |
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check_cp14_access (ARMul_State * state, |
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unsigned reg, |
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unsigned CRm, unsigned opcode1, unsigned opcode2) |
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{ |
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/* Not allowed to access these register in USER mode. */ |
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//chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
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if (state->Mode == USER26MODE || state->Mode == USER32MODE ) |
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return ARMul_CANT; |
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/* CRm should be zero. */ |
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if (CRm != 0) |
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return ARMul_CANT; |
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/* OPcodes should be zero. */ |
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if (opcode1 != 0 || opcode2 != 0) |
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return ARMul_CANT; |
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/* Accessing registers 4 or 5 has unpredicatable results. */ |
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if (reg >= 4 && reg <= 5) |
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return ARMul_CANT; |
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return ARMul_DONE; |
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} |
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/* Here's ARMulator's MMU definition. A few things to note:
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1) It has eight registers, but only two are defined. |
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2) You can only access its registers with MCR and MRC. |
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3) MMU Register 0 (ID) returns 0x41440110 |
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4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4 |
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controls 32/26 bit program space, bit 5 controls 32/26 bit data space, |
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bit 6 controls late abort timimg and bit 7 controls big/little endian. */ |
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static ARMword MMUReg[8]; |
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static unsigned |
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MMUInit (ARMul_State * state) |
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{ |
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/* 2004-05-09 chy
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------------------------------------------------------------- |
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read ARM Architecture Reference Manual |
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2.6.5 Data Abort |
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There are three Abort Model in ARM arch. |
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Early Abort Model: used in some ARMv3 and earlier implementations. In this |
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model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and |
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the base register was unchanged for all other instructions. (oldest) |
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Base Restored Abort Model: If a Data Abort occurs in an instruction which |
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specifies base register writeback, the value in the base register is |
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unchanged. (strongarm, xscale) |
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||||
|
Base Updated Abort Model: If a Data Abort occurs in an instruction which |
||||
|
specifies base register writeback, the base register writeback still occurs. |
||||
|
(arm720T) |
||||
|
|
||||
|
read PART B |
||||
|
chap2 The System Control Coprocessor CP15 |
||||
|
2.4 Register1:control register |
||||
|
L(bit 6): in some ARMv3 and earlier implementations, the abort model of the |
||||
|
processor could be configured: |
||||
|
0=early Abort Model Selected(now obsolete) |
||||
|
1=Late Abort Model selceted(same as Base Updated Abort Model) |
||||
|
|
||||
|
on later processors, this bit reads as 1 and ignores writes. |
||||
|
------------------------------------------------------------- |
||||
|
So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) |
||||
|
if lateabtSig=0, then it means Base Restored Abort Model |
||||
|
because the ARMs which skyeye simulates are all belonged to ARMv4, |
||||
|
so I think MMUReg[1]'s bit 6 should always be 1 |
||||
|
|
||||
|
*/ |
||||
|
|
||||
|
MMUReg[1] = state->prog32Sig << 4 | |
||||
|
state->data32Sig << 5 | 1 << 6 | state->bigendSig << 7; |
||||
|
//state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
|
||||
|
|
||||
|
|
||||
|
ARMul_ConsolePrint (state, ", MMU present"); |
||||
|
|
||||
|
return TRUE; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
MMUMRC (ARMul_State * state, unsigned type, |
||||
|
ARMword instr, ARMword * value) |
||||
|
{ |
||||
|
mmu_mrc (state, instr, value); |
||||
|
return (ARMul_DONE); |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
MMUMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value) |
||||
|
{ |
||||
|
mmu_mcr (state, instr, value); |
||||
|
return (ARMul_DONE); |
||||
|
} |
||||
|
|
||||
|
/* What follows is the Validation Suite Coprocessor. It uses two
|
||||
|
co-processor numbers (4 and 5) and has the follwing functionality. |
||||
|
Sixteen registers. Both co-processor nuimbers can be used in an MCR |
||||
|
and MRC to access these registers. CP 4 can LDC and STC to and from |
||||
|
the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of |
||||
|
cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a |
||||
|
number of cycles (specified in a CP register), CDP 2 issues an IRQW |
||||
|
in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 |
||||
|
stores a 32 bit time value in a CP register (actually it's the total |
||||
|
number of N, S, I, C and F cyles). */ |
||||
|
|
||||
|
static ARMword ValReg[16]; |
||||
|
|
||||
|
static unsigned |
||||
|
ValLDC (ARMul_State * state, |
||||
|
unsigned type, ARMword instr, ARMword data) |
||||
|
{ |
||||
|
static unsigned words; |
||||
|
|
||||
|
if (type != ARMul_DATA) |
||||
|
words = 0; |
||||
|
else { |
||||
|
ValReg[BITS (12, 15)] = data; |
||||
|
|
||||
|
if (BIT (22)) |
||||
|
/* It's a long access, get two words. */ |
||||
|
if (words++ != 4) |
||||
|
return ARMul_INC; |
||||
|
} |
||||
|
|
||||
|
return ARMul_DONE; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
ValSTC (ARMul_State * state, |
||||
|
unsigned type, ARMword instr, ARMword * data) |
||||
|
{ |
||||
|
static unsigned words; |
||||
|
|
||||
|
if (type != ARMul_DATA) |
||||
|
words = 0; |
||||
|
else { |
||||
|
*data = ValReg[BITS (12, 15)]; |
||||
|
|
||||
|
if (BIT (22)) |
||||
|
/* It's a long access, get two words. */ |
||||
|
if (words++ != 4) |
||||
|
return ARMul_INC; |
||||
|
} |
||||
|
|
||||
|
return ARMul_DONE; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
ValMRC (ARMul_State * state, |
||||
|
unsigned type, ARMword instr, ARMword * value) |
||||
|
{ |
||||
|
*value = ValReg[BITS (16, 19)]; |
||||
|
|
||||
|
return ARMul_DONE; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
ValMCR (ARMul_State * state, |
||||
|
unsigned type, ARMword instr, ARMword value) |
||||
|
{ |
||||
|
ValReg[BITS (16, 19)] = value; |
||||
|
|
||||
|
return ARMul_DONE; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
ValCDP (ARMul_State * state, unsigned type, ARMword instr) |
||||
|
{ |
||||
|
static unsigned int finish = 0; |
||||
|
|
||||
|
if (BITS (20, 23) != 0) |
||||
|
return ARMul_CANT; |
||||
|
|
||||
|
if (type == ARMul_FIRST) { |
||||
|
ARMword howlong; |
||||
|
|
||||
|
howlong = ValReg[BITS (0, 3)]; |
||||
|
|
||||
|
/* First cycle of a busy wait. */ |
||||
|
finish = ARMul_Time (state) + howlong; |
||||
|
|
||||
|
return howlong == 0 ? ARMul_DONE : ARMul_BUSY; |
||||
|
} |
||||
|
else if (type == ARMul_BUSY) { |
||||
|
if (ARMul_Time (state) >= finish) |
||||
|
return ARMul_DONE; |
||||
|
else |
||||
|
return ARMul_BUSY; |
||||
|
} |
||||
|
|
||||
|
return ARMul_CANT; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
DoAFIQ (ARMul_State * state) |
||||
|
{ |
||||
|
state->NfiqSig = LOW; |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
DoAIRQ (ARMul_State * state) |
||||
|
{ |
||||
|
state->NirqSig = LOW; |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
static unsigned |
||||
|
IntCDP (ARMul_State * state, unsigned type, ARMword instr) |
||||
|
{ |
||||
|
static unsigned int finish; |
||||
|
ARMword howlong; |
||||
|
|
||||
|
howlong = ValReg[BITS (0, 3)]; |
||||
|
|
||||
|
switch ((int) BITS (20, 23)) { |
||||
|
case 0: |
||||
|
if (type == ARMul_FIRST) { |
||||
|
/* First cycle of a busy wait. */ |
||||
|
finish = ARMul_Time (state) + howlong; |
||||
|
|
||||
|
return howlong == 0 ? ARMul_DONE : ARMul_BUSY; |
||||
|
} |
||||
|
else if (type == ARMul_BUSY) { |
||||
|
if (ARMul_Time (state) >= finish) |
||||
|
return ARMul_DONE; |
||||
|
else |
||||
|
return ARMul_BUSY; |
||||
|
} |
||||
|
return ARMul_DONE; |
||||
|
|
||||
|
case 1: |
||||
|
if (howlong == 0) |
||||
|
ARMul_Abort (state, ARMul_FIQV); |
||||
|
else |
||||
|
ARMul_ScheduleEvent (state, howlong, DoAFIQ); |
||||
|
return ARMul_DONE; |
||||
|
|
||||
|
case 2: |
||||
|
if (howlong == 0) |
||||
|
ARMul_Abort (state, ARMul_IRQV); |
||||
|
else |
||||
|
ARMul_ScheduleEvent (state, howlong, DoAIRQ); |
||||
|
return ARMul_DONE; |
||||
|
|
||||
|
case 3: |
||||
|
state->NfiqSig = HIGH; |
||||
|
return ARMul_DONE; |
||||
|
|
||||
|
case 4: |
||||
|
state->NirqSig = HIGH; |
||||
|
return ARMul_DONE; |
||||
|
|
||||
|
case 5: |
||||
|
ValReg[BITS (0, 3)] = ARMul_Time (state); |
||||
|
return ARMul_DONE; |
||||
|
} |
||||
|
|
||||
|
return ARMul_CANT; |
||||
|
} |
||||
|
|
||||
|
/* Install co-processor instruction handlers in this routine. */ |
||||
|
|
||||
|
unsigned |
||||
|
ARMul_CoProInit (ARMul_State * state) |
||||
|
{ |
||||
|
unsigned int i; |
||||
|
|
||||
|
/* Initialise tham all first. */ |
||||
|
for (i = 0; i < 16; i++) |
||||
|
ARMul_CoProDetach (state, i); |
||||
|
|
||||
|
/* Install CoPro Instruction handlers here.
|
||||
|
The format is: |
||||
|
ARMul_CoProAttach (state, CP Number, Init routine, Exit routine |
||||
|
LDC routine, STC routine, MRC routine, MCR routine, |
||||
|
CDP routine, Read Reg routine, Write Reg routine). */ |
||||
|
if (state->is_ep9312) { |
||||
|
ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4, |
||||
|
DSPMRC4, DSPMCR4, NULL, NULL, DSPCDP4, NULL, NULL); |
||||
|
ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5, |
||||
|
DSPMRC5, DSPMCR5, NULL, NULL, DSPCDP5, NULL, NULL); |
||||
|
ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL, |
||||
|
DSPMRC6, DSPMCR6, NULL, NULL, DSPCDP6, NULL, NULL); |
||||
|
} |
||||
|
else { |
||||
|
ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC, |
||||
|
ValMRC, ValMCR, NULL, NULL, ValCDP, NULL, NULL); |
||||
|
|
||||
|
ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL, |
||||
|
ValMRC, ValMCR, NULL, NULL, IntCDP, NULL, NULL); |
||||
|
} |
||||
|
|
||||
|
if (state->is_XScale) { |
||||
|
//chy 2005-09-19, for PXA27x's CP6
|
||||
|
if (state->is_pxa27x) { |
||||
|
ARMul_CoProAttach (state, 6, NULL, NULL, |
||||
|
NULL, NULL, xscale_cp6_mrc, |
||||
|
NULL, NULL, NULL, NULL, NULL, NULL); |
||||
|
} |
||||
|
//chy 2005-09-19 end-------------
|
||||
|
ARMul_CoProAttach (state, 13, xscale_cp13_init, |
||||
|
xscale_cp13_exit, xscale_cp13_ldc, |
||||
|
xscale_cp13_stc, xscale_cp13_mrc, |
||||
|
xscale_cp13_mcr, NULL, NULL, xscale_cp13_cdp, |
||||
|
xscale_cp13_read_reg, |
||||
|
xscale_cp13_write_reg); |
||||
|
|
||||
|
ARMul_CoProAttach (state, 14, xscale_cp14_init, |
||||
|
xscale_cp14_exit, xscale_cp14_ldc, |
||||
|
xscale_cp14_stc, xscale_cp14_mrc, |
||||
|
xscale_cp14_mcr, NULL, NULL, xscale_cp14_cdp, |
||||
|
xscale_cp14_read_reg, |
||||
|
xscale_cp14_write_reg); |
||||
|
//chy: 2003-08-24.
|
||||
|
ARMul_CoProAttach (state, 15, xscale_cp15_init, |
||||
|
xscale_cp15_exit, xscale_cp15_ldc, |
||||
|
xscale_cp15_stc, xscale_cp15_mrc, |
||||
|
xscale_cp15_mcr, NULL, NULL, xscale_cp15_cdp, |
||||
|
xscale_cp15_read_reg, |
||||
|
xscale_cp15_write_reg); |
||||
|
} |
||||
|
else if (state->is_v6) { |
||||
|
ARMul_CoProAttach (state, 10, VFPInit, NULL, VFPLDC, VFPSTC, |
||||
|
VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL); |
||||
|
ARMul_CoProAttach (state, 11, VFPInit, NULL, VFPLDC, VFPSTC, |
||||
|
VFPMRC, VFPMCR, VFPMRRC, VFPMCRR, VFPCDP, NULL, NULL); |
||||
|
|
||||
|
ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, |
||||
|
MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL); |
||||
|
} |
||||
|
else { //all except xscale
|
||||
|
ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL, |
||||
|
// MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
|
||||
|
MMUMRC, MMUMCR, NULL, NULL, NULL, NULL, NULL); |
||||
|
} |
||||
|
//chy 2003-09-03 do it in future!!!!????
|
||||
|
#if 0
|
||||
|
if (state->is_iWMMXt) { |
||||
|
ARMul_CoProAttach (state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC, |
||||
|
NULL, NULL, IwmmxtCDP, NULL, NULL); |
||||
|
|
||||
|
ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL, |
||||
|
IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, |
||||
|
NULL); |
||||
|
} |
||||
|
#endif
|
||||
|
//-----------------------------------------------------------------------------
|
||||
|
//chy 2004-05-25, found the user/system code visit CP 1,2, so I add below code.
|
||||
|
ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL, |
||||
|
ValMRC, ValMCR, NULL, NULL, NULL, NULL, NULL); |
||||
|
ARMul_CoProAttach (state, 2, NULL, NULL, ValLDC, ValSTC, |
||||
|
NULL, NULL, NULL, NULL, NULL, NULL, NULL); |
||||
|
//------------------------------------------------------------------------------
|
||||
|
/* No handlers below here. */ |
||||
|
|
||||
|
/* Call all the initialisation routines. */ |
||||
|
for (i = 0; i < 16; i++) |
||||
|
if (state->CPInit[i]) |
||||
|
(state->CPInit[i]) (state); |
||||
|
|
||||
|
return TRUE; |
||||
|
} |
||||
|
|
||||
|
/* Install co-processor finalisation routines in this routine. */ |
||||
|
|
||||
|
void |
||||
|
ARMul_CoProExit (ARMul_State * state) |
||||
|
{ |
||||
|
register unsigned i; |
||||
|
|
||||
|
for (i = 0; i < 16; i++) |
||||
|
if (state->CPExit[i]) |
||||
|
(state->CPExit[i]) (state); |
||||
|
|
||||
|
for (i = 0; i < 16; i++) /* Detach all handlers. */ |
||||
|
ARMul_CoProDetach (state, i); |
||||
|
} |
||||
|
|
||||
|
/* Routines to hook Co-processors into ARMulator. */ |
||||
|
|
||||
|
void |
||||
|
ARMul_CoProAttach (ARMul_State * state, |
||||
|
unsigned number, |
||||
|
ARMul_CPInits * init, |
||||
|
ARMul_CPExits * exit, |
||||
|
ARMul_LDCs * ldc, |
||||
|
ARMul_STCs * stc, |
||||
|
ARMul_MRCs * mrc, |
||||
|
ARMul_MCRs * mcr, |
||||
|
ARMul_MRRCs * mrrc, |
||||
|
ARMul_MCRRs * mcrr, |
||||
|
ARMul_CDPs * cdp, |
||||
|
ARMul_CPReads * read, ARMul_CPWrites * write) |
||||
|
{ |
||||
|
if (init != NULL) |
||||
|
state->CPInit[number] = init; |
||||
|
if (exit != NULL) |
||||
|
state->CPExit[number] = exit; |
||||
|
if (ldc != NULL) |
||||
|
state->LDC[number] = ldc; |
||||
|
if (stc != NULL) |
||||
|
state->STC[number] = stc; |
||||
|
if (mrc != NULL) |
||||
|
state->MRC[number] = mrc; |
||||
|
if (mcr != NULL) |
||||
|
state->MCR[number] = mcr; |
||||
|
if (mrrc != NULL) |
||||
|
state->MRRC[number] = mrrc; |
||||
|
if (mcrr != NULL) |
||||
|
state->MCRR[number] = mcrr; |
||||
|
if (cdp != NULL) |
||||
|
state->CDP[number] = cdp; |
||||
|
if (read != NULL) |
||||
|
state->CPRead[number] = read; |
||||
|
if (write != NULL) |
||||
|
state->CPWrite[number] = write; |
||||
|
} |
||||
|
|
||||
|
void |
||||
|
ARMul_CoProDetach (ARMul_State * state, unsigned number) |
||||
|
{ |
||||
|
ARMul_CoProAttach (state, number, NULL, NULL, |
||||
|
NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R, |
||||
|
NoCoPro5W, NoCoPro5R, NoCoPro3R, NULL, NULL); |
||||
|
|
||||
|
state->CPInit[number] = NULL; |
||||
|
state->CPExit[number] = NULL; |
||||
|
state->CPRead[number] = NULL; |
||||
|
state->CPWrite[number] = NULL; |
||||
|
} |
||||
|
|
||||
|
//chy 2003-09-03:below funs just replace the old ones
|
||||
|
|
||||
|
/* Set the XScale FSR and FAR registers. */ |
||||
|
|
||||
|
void |
||||
|
XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far) |
||||
|
{ |
||||
|
//if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
|
||||
|
if (!state->is_XScale) |
||||
|
return; |
||||
|
//assume opcode2=0 crm =0
|
||||
|
xscale_cp15_write_reg (state, 5, fsr); |
||||
|
xscale_cp15_write_reg (state, 6, _far); |
||||
|
} |
||||
|
|
||||
|
//chy 2003-09-03 seems 0 is CANT, 1 is DONE ????
|
||||
|
int |
||||
|
XScale_debug_moe (ARMul_State * state, int moe) |
||||
|
{ |
||||
|
//chy 2003-09-03 , W/R CP14 reg, now it's no use ????
|
||||
|
printf ("SKYEYE: XScale_debug_moe called !!!!\n"); |
||||
|
return 1; |
||||
|
} |
||||
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