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@ -90,6 +90,20 @@ public: |
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enum class QuerySelect : u32 { |
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Zero = 0, |
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TimeElapsed = 2, |
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TransformFeedbackPrimitivesGenerated = 11, |
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PrimitivesGenerated = 18, |
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SamplesPassed = 21, |
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TransformFeedbackUnknown = 26, |
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}; |
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struct QueryCompare { |
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u32 initial_sequence; |
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u32 initial_mode; |
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u32 unknown1; |
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u32 unknown2; |
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u32 current_sequence; |
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u32 current_mode; |
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}; |
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enum class QuerySyncCondition : u32 { |
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@ -97,6 +111,14 @@ public: |
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GreaterThan = 1, |
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}; |
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enum class ConditionMode : u32 { |
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Never = 0, |
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Always = 1, |
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ResNonZero = 2, |
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Equal = 3, |
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NotEqual = 4, |
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}; |
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enum class ShaderProgram : u32 { |
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VertexA = 0, |
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VertexB = 1, |
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@ -815,7 +837,18 @@ public: |
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BitField<4, 1, u32> alpha_to_one; |
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} multisample_control; |
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INSERT_PADDING_WORDS(0x7); |
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INSERT_PADDING_WORDS(0x4); |
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struct { |
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u32 address_high; |
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u32 address_low; |
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ConditionMode mode; |
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GPUVAddr Address() const { |
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | |
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address_low); |
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} |
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} condition; |
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struct { |
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u32 tsc_address_high; |
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@ -1223,6 +1256,10 @@ public: |
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return macro_memory; |
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} |
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bool ShouldExecute() const { |
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return execute_on; |
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} |
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private: |
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void InitializeRegisterDefaults(); |
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@ -1257,6 +1294,8 @@ private: |
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Upload::State upload_state; |
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bool execute_on{true}; |
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/// Retrieves information about a specific TIC entry from the TIC buffer. |
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Texture::TICEntry GetTICEntry(u32 tic_index) const; |
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@ -1284,6 +1323,9 @@ private: |
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/// Handles a write to the QUERY_GET register. |
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void ProcessQueryGet(); |
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// Handles Conditional Rendering |
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void ProcessQueryCondition(); |
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/// Handles writes to syncing register. |
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void ProcessSyncPoint(); |
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@ -1357,6 +1399,7 @@ ASSERT_REG_POSITION(clip_distance_enabled, 0x544); |
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ASSERT_REG_POSITION(point_size, 0x546); |
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ASSERT_REG_POSITION(zeta_enable, 0x54E); |
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ASSERT_REG_POSITION(multisample_control, 0x54F); |
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ASSERT_REG_POSITION(condition, 0x554); |
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ASSERT_REG_POSITION(tsc, 0x557); |
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ASSERT_REG_POSITION(polygon_offset_factor, 0x55b); |
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ASSERT_REG_POSITION(tic, 0x55D); |
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