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@ -51,23 +51,35 @@ enum { |
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TOP_WIDTH = 400, |
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BOTTOM_WIDTH = 320, |
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// Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware |
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PADDR_FRAMEBUFFER_SEL = 0x20184E59, |
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PADDR_TOP_LEFT_FRAME1 = 0x20184E60, |
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// Physical addresses in FCRAM (chosen arbitrarily) |
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PADDR_TOP_LEFT_FRAME1 = 0x201D4C00, |
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PADDR_TOP_LEFT_FRAME2 = 0x202D4C00, |
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PADDR_TOP_RIGHT_FRAME1 = 0x203D4C00, |
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PADDR_TOP_RIGHT_FRAME2 = 0x204D4C00, |
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PADDR_SUB_FRAME1 = 0x205D4C00, |
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PADDR_SUB_FRAME2 = 0x206D4C00, |
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// Physical addresses in FCRAM used by ARM9 applications |
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/* PADDR_TOP_LEFT_FRAME1 = 0x20184E60, |
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PADDR_TOP_LEFT_FRAME2 = 0x201CB370, |
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PADDR_TOP_RIGHT_FRAME1 = 0x20282160, |
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PADDR_TOP_RIGHT_FRAME2 = 0x202C8670, |
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PADDR_SUB_FRAME1 = 0x202118E0, |
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PADDR_SUB_FRAME2 = 0x20249CF0, |
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// Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real) |
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PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59, |
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PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60, |
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PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, |
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PADDR_SUB_FRAME2 = 0x20249CF0,*/ |
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// Physical addresses in VRAM |
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// TODO: These should just be deduced from the ones above |
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PADDR_VRAM_TOP_LEFT_FRAME1 = 0x181D4C00, |
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PADDR_VRAM_TOP_LEFT_FRAME2 = 0x182D4C00, |
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PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x183D4C00, |
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PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x184D4C00, |
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PADDR_VRAM_SUB_FRAME1 = 0x185D4C00, |
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PADDR_VRAM_SUB_FRAME2 = 0x186D4C00, |
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// Physical addresses in VRAM used by ARM9 applications |
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/* PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370, |
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PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160, |
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PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670, |
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PADDR_VRAM_SUB_FRAME1 = 0x182118E0, |
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PADDR_VRAM_SUB_FRAME2 = 0x18249CF0, |
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PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,*/ |
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}; |
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/// Framebuffer location |
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