ReinUsesLisp
5 years ago
committed by
ameerj
ameerj
12 changed files with 400 additions and 42 deletions
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1src/shader_recompiler/CMakeLists.txt
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28src/shader_recompiler/backend/spirv/emit_spirv.h
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72src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
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16src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
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90src/shader_recompiler/frontend/ir/ir_emitter.cpp
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4src/shader_recompiler/frontend/ir/ir_emitter.h
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17src/shader_recompiler/frontend/ir/opcodes.inc
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184src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_add.cpp
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2src/shader_recompiler/frontend/maxwell/translate/impl/load_store_memory.cpp
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16src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
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2src/shader_recompiler/ir_opt/global_memory_to_storage_buffer_pass.cpp
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10src/shader_recompiler/ir_opt/lower_fp16_to_fp32.cpp
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/common_types.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell { |
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namespace { |
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enum class Merge : u64 { |
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H1_H0, |
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F32, |
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MRG_H0, |
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MRG_H1, |
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}; |
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enum class Swizzle : u64 { |
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H1_H0, |
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F32, |
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H0_H0, |
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H1_H1, |
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}; |
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std::pair<IR::F16F32F64, IR::F16F32F64> Extract(IR::IREmitter& ir, IR::U32 value, Swizzle swizzle) { |
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switch (swizzle) { |
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case Swizzle::H1_H0: { |
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const IR::Value vector{ir.UnpackFloat2x16(value)}; |
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return {IR::F16{ir.CompositeExtract(vector, 0)}, IR::F16{ir.CompositeExtract(vector, 1)}}; |
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} |
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case Swizzle::H0_H0: { |
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const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 0)}; |
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return {scalar, scalar}; |
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} |
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case Swizzle::H1_H1: { |
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const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 1)}; |
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return {scalar, scalar}; |
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} |
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case Swizzle::F32: { |
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const IR::F32 scalar{ir.BitCast<IR::F32>(value)}; |
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return {scalar, scalar}; |
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} |
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} |
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throw InvalidArgument("Invalid swizzle {}", swizzle); |
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} |
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IR::U32 MergeResult(IR::IREmitter& ir, IR::Reg dest, const IR::F16& lhs, const IR::F16& rhs, |
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Merge merge) { |
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switch (merge) { |
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case Merge::H1_H0: |
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return ir.PackFloat2x16(ir.CompositeConstruct(lhs, rhs)); |
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case Merge::F32: |
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return ir.BitCast<IR::U32, IR::F32>(ir.FPConvert(32, lhs)); |
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case Merge::MRG_H0: |
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case Merge::MRG_H1: { |
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const IR::Value vector{ir.UnpackFloat2x16(ir.GetReg(dest))}; |
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const bool h0{merge == Merge::MRG_H0}; |
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const IR::F16& insert{h0 ? lhs : rhs}; |
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return ir.PackFloat2x16(ir.CompositeInsert(vector, insert, h0 ? 0 : 1)); |
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} |
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} |
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throw InvalidArgument("Invalid merge {}", merge); |
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} |
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void HADD2(TranslatorVisitor& v, u64 insn, Merge merge, bool ftz, bool sat, bool abs_a, bool neg_a, |
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Swizzle swizzle_a, bool abs_b, bool neg_b, Swizzle swizzle_b, const IR::U32& src_b) { |
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union { |
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u64 raw; |
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BitField<0, 8, IR::Reg> dest_reg; |
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BitField<8, 8, IR::Reg> src_a; |
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} const hadd2{insn}; |
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auto [lhs_a, rhs_a]{Extract(v.ir, v.X(hadd2.src_a), swizzle_a)}; |
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auto [lhs_b, rhs_b]{Extract(v.ir, src_b, swizzle_b)}; |
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const bool promotion{lhs_a.Type() != lhs_b.Type()}; |
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if (promotion) { |
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if (lhs_a.Type() == IR::Type::F16) { |
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lhs_a = v.ir.FPConvert(32, lhs_a); |
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rhs_a = v.ir.FPConvert(32, rhs_a); |
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} |
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if (lhs_b.Type() == IR::Type::F16) { |
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lhs_b = v.ir.FPConvert(32, lhs_b); |
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rhs_b = v.ir.FPConvert(32, rhs_b); |
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} |
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} |
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lhs_a = v.ir.FPAbsNeg(lhs_a, abs_a, neg_a); |
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rhs_a = v.ir.FPAbsNeg(rhs_a, abs_a, neg_a); |
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lhs_b = v.ir.FPAbsNeg(lhs_b, abs_b, neg_b); |
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rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b); |
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const IR::FpControl fp_control{ |
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.no_contraction{true}, |
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.rounding{IR::FpRounding::DontCare}, |
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.fmz_mode{ftz ? IR::FmzMode::FTZ : IR::FmzMode::None}, |
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}; |
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IR::F16F32F64 lhs{v.ir.FPAdd(lhs_a, lhs_b, fp_control)}; |
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IR::F16F32F64 rhs{v.ir.FPAdd(rhs_a, rhs_b, fp_control)}; |
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if (sat) { |
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lhs = v.ir.FPSaturate(lhs); |
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rhs = v.ir.FPSaturate(rhs); |
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} |
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if (promotion) { |
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lhs = v.ir.FPConvert(16, lhs); |
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rhs = v.ir.FPConvert(16, rhs); |
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} |
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v.X(hadd2.dest_reg, MergeResult(v.ir, hadd2.dest_reg, lhs, rhs, merge)); |
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} |
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} // Anonymous namespace
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void TranslatorVisitor::HADD2_reg(u64 insn) { |
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union { |
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u64 raw; |
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BitField<49, 2, Merge> merge; |
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BitField<39, 1, u64> ftz; |
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BitField<32, 1, u64> sat; |
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BitField<43, 1, u64> neg_a; |
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BitField<44, 1, u64> abs_a; |
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BitField<47, 2, Swizzle> swizzle_a; |
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BitField<31, 1, u64> neg_b; |
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BitField<30, 1, u64> abs_b; |
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BitField<28, 2, Swizzle> swizzle_b; |
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} const hadd2{insn}; |
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HADD2(*this, insn, hadd2.merge, hadd2.ftz != 0, hadd2.sat != 0, hadd2.abs_a != 0, |
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hadd2.neg_a != 0, hadd2.swizzle_a, hadd2.abs_b != 0, hadd2.neg_b != 0, hadd2.swizzle_b, |
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GetReg20(insn)); |
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} |
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void TranslatorVisitor::HADD2_cbuf(u64 insn) { |
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union { |
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u64 raw; |
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BitField<49, 2, Merge> merge; |
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BitField<39, 1, u64> ftz; |
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BitField<52, 1, u64> sat; |
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BitField<43, 1, u64> neg_a; |
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BitField<44, 1, u64> abs_a; |
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BitField<47, 2, Swizzle> swizzle_a; |
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BitField<56, 1, u64> neg_b; |
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BitField<54, 1, u64> abs_b; |
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} const hadd2{insn}; |
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HADD2(*this, insn, hadd2.merge, hadd2.ftz != 0, hadd2.sat != 0, hadd2.abs_a != 0, |
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hadd2.neg_a != 0, hadd2.swizzle_a, hadd2.abs_b != 0, hadd2.neg_b != 0, Swizzle::F32, |
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GetCbuf(insn)); |
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} |
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void TranslatorVisitor::HADD2_imm(u64 insn) { |
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union { |
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u64 raw; |
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BitField<49, 2, Merge> merge; |
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BitField<39, 1, u64> ftz; |
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BitField<52, 1, u64> sat; |
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BitField<43, 1, u64> neg_a; |
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BitField<44, 1, u64> abs_a; |
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BitField<47, 2, Swizzle> swizzle_a; |
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BitField<56, 1, u64> neg_high; |
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BitField<30, 9, u64> high; |
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BitField<29, 1, u64> neg_low; |
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BitField<20, 9, u64> low; |
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} const hadd2{insn}; |
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const u32 imm{static_cast<u32>(hadd2.low << 6) | ((hadd2.neg_low != 0 ? 1 : 0) << 15) | |
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static_cast<u32>(hadd2.high << 22) | ((hadd2.neg_high != 0 ? 1 : 0) << 31)}; |
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HADD2(*this, insn, hadd2.merge, hadd2.ftz != 0, hadd2.sat != 0, hadd2.abs_a != 0, |
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hadd2.neg_a != 0, hadd2.swizzle_a, false, false, Swizzle::H1_H0, ir.Imm32(imm)); |
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} |
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void TranslatorVisitor::HADD2_32I(u64 insn) { |
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union { |
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u64 raw; |
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BitField<55, 1, u64> ftz; |
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BitField<52, 1, u64> sat; |
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BitField<56, 1, u64> neg_a; |
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BitField<53, 2, Swizzle> swizzle_a; |
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BitField<20, 32, u64> imm32; |
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} const hadd2{insn}; |
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const u32 imm{static_cast<u32>(hadd2.imm32)}; |
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HADD2(*this, insn, Merge::H1_H0, hadd2.ftz != 0, hadd2.sat != 0, false, hadd2.neg_a != 0, |
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hadd2.swizzle_a, false, false, Swizzle::H1_H0, ir.Imm32(imm)); |
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} |
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} // namespace Shader::Maxwell
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