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@ -13,7 +13,7 @@ namespace Tegra { |
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namespace Shader { |
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struct Register { |
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Register() = default; |
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constexpr Register() = default; |
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constexpr Register(u64 value) : value(value) {} |
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@ -40,13 +40,13 @@ struct Register { |
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} |
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private: |
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u64 value; |
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u64 value{}; |
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}; |
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union Attribute { |
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Attribute() = default; |
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constexpr Attribute(u64 value) : value(value) {} |
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constexpr explicit Attribute(u64 value) : value(value) {} |
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enum class Index : u64 { |
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Position = 7, |
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@ -65,20 +65,20 @@ union Attribute { |
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} fmt28; |
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BitField<39, 8, u64> reg; |
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u64 value; |
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u64 value{}; |
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}; |
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union Sampler { |
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Sampler() = default; |
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constexpr Sampler(u64 value) : value(value) {} |
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constexpr explicit Sampler(u64 value) : value(value) {} |
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enum class Index : u64 { |
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Sampler_0 = 8, |
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}; |
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BitField<36, 13, Index> index; |
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u64 value; |
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u64 value{}; |
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}; |
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union Uniform { |
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@ -248,7 +248,7 @@ union OpCode { |
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BitField<55, 9, Id> op3; |
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BitField<52, 12, Id> op4; |
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BitField<51, 13, Id> op5; |
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u64 value; |
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u64 value{}; |
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}; |
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static_assert(sizeof(OpCode) == 0x8, "Incorrect structure size"); |
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