diff --git a/src/dynarmic/README.md b/src/dynarmic/README.md
index 38248a0dc2..71aa6f8703 100644
--- a/src/dynarmic/README.md
+++ b/src/dynarmic/README.md
@@ -35,6 +35,7 @@ There are no plans to support v1 or v2.
 
 * x86-64
 * AArch64
+* PowerPC 64 (POWER 4 and up)
 
 There are no plans to support any 32-bit architecture.
 
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
index 5e56789fb5..bc47dcedc1 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/a64_interface.cpp
@@ -81,6 +81,7 @@ struct Jit::Impl final {
         ASSERT(!is_executing);
         is_executing = true;
         HaltReason hr = core.Run(current_address_space, jit_state, &halt_reason);
+        current_address_space.ClearCache(); // TODO: dont just invalidate everything
         is_executing = false;
         RequestCacheInvalidation();
         return hr;
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
index e6da30be82..d463c7c069 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64.cpp
@@ -182,8 +182,8 @@ void EmitTerminal(powah::Context& code, EmitContext& ctx, IR::Term::CheckBit ter
     powah::Label const l_else = code.DefineLabel();
     powah::Label const l_end = code.DefineLabel();
     auto const tmp = ctx.reg_alloc.ScratchGpr();
-    code.LBZ(tmp, PPC64::RJIT, ctx.emit_conf.a64_variant ? offsetof(A64JitState, check_bit) : offsetof(A32JitState, check_bit));
-    code.CMPLWI(tmp, 0);
+    code.LD(tmp, powah::R1, offsetof(StackLayout, check_bit));
+    code.CMPLDI(tmp, 0);
     code.BEQ(powah::CR0, l_else);
     // CheckBit == 1
     EmitTerminal(code, ctx, terminal.then_, initial_location, is_single_step);
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
index 0ed9a09c6e..b341373d61 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/emit_ppc64_a64.cpp
@@ -19,7 +19,7 @@ namespace Dynarmic::Backend::PPC64 {
 template<>
 void EmitIR<IR::Opcode::A64SetCheckBit>(powah::Context& code, EmitContext& ctx, IR::Inst* inst) {
     auto const value = ctx.reg_alloc.UseGpr(inst->GetArg(0));
-    code.STB(value, PPC64::RJIT, offsetof(A64JitState, check_bit));
+    code.STD(value, powah::R1, offsetof(StackLayout, check_bit));
 }
 
 template<>
diff --git a/src/dynarmic/src/dynarmic/backend/ppc64/stack_layout.h b/src/dynarmic/src/dynarmic/backend/ppc64/stack_layout.h
index bb70a359a9..9b83d971d6 100644
--- a/src/dynarmic/src/dynarmic/backend/ppc64/stack_layout.h
+++ b/src/dynarmic/src/dynarmic/backend/ppc64/stack_layout.h
@@ -9,18 +9,12 @@
 
 namespace Dynarmic::Backend::PPC64 {
 
-constexpr size_t SpillCount = 64;
+constexpr size_t SpillCount = 16;
 
 struct alignas(16) StackLayout {
-    s64 cycles_remaining;
-    s64 cycles_to_run;
-
+    std::array<u64, 18> regs;
     std::array<u64, SpillCount> spill;
-
-    u32 save_host_fpcr;
-    u32 save_host_fpsr;
-
-    bool check_bit;
+    u64 check_bit;
 };
 
 static_assert(sizeof(StackLayout) % 16 == 0);